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components/74x1g04_6.lib: add single inverter; update HIERARCHY
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@ -41,6 +41,7 @@ Werner Almesberger <werner@almesberger.net>
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components/8_10-card.lib
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components/vga.lib
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components/74x1g04_6.lib
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components/74x1g08_5.lib (based on 74x1g00_5.lib)
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components/74x1g08_6.lib (based on 74x1g00_5.lib)
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components/74x1g07_5.lib
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components/74x1g04_6.dcm
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components/74x1g04_6.dcm
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@ -0,0 +1,7 @@
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EESchema-DOCLIB Version 2.0
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#
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$CMP 74X1G04_6
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D Single inverter in 6 pin package.
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$ENDCMP
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#
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#End Doc Library
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components/74x1g04_6.lib
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components/74x1g04_6.lib
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# 74X1G04_6
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#
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DEF 74X1G04_6 U 0 0 Y Y 1 F N
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F0 "U" -200 200 60 H V C CNN
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F1 "74X1G04_6" 100 -150 60 H V L CNN
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F2 "" -150 175 60 H I C CNN
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F3 "" -150 175 60 H I C CNN
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DRAW
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C 75 0 25 0 1 0 N
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P 2 0 1 0 0 -50 0 -35 N
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P 2 0 1 0 0 50 0 35 N
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P 4 0 1 0 -100 -100 -100 100 50 0 -100 -100 N
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X NC 1 300 150 200 L 50 40 1 1 N N
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X A 2 -300 0 200 R 50 50 1 1 I
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X GND 3 0 -250 200 U 50 40 1 1 W
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X Y 4 300 0 200 L 50 50 1 1 O
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X NC 5 300 100 200 L 50 40 1 1 N N
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X VCC 6 0 250 200 D 50 40 1 1 W
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ENDDRAW
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ENDDEF
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#
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#End Library
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@ -16,15 +16,19 @@ Passive
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Logic
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Single
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74x1g00_5
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74x1g04_6
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74x1g07_4
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74x1g07_5
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74x1g07_6
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74x1g07_6
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74x1g08_5
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74x1g08_6
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74x1g32_6
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74x1g32_6-LARGE
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74x1g125
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Dual
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74x2g07_6
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74x2g07_6-LARGE
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74x2g126
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Shift
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74x595
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@ -170,3 +170,4 @@ LibName98=./tps6102x
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LibName99=./gencon
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LibName100=./74x2g07_6
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LibName101=./74x1g32_6
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LibName102=./74x1g04_6
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