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1f0d15cc80
NXP put "R" as the first name of some pins, e.g., R/PIO1_2/AD3/CT32B1_MAT This is meant to indicate that it may have a possible extra function which doesn't exist in the present implementation. The whole concept seems bogus. First of all, there are several pins with supposedly different roles but all with a common name. Second, one isn't even supposed to set the pin configuration register to a value selecting this "reserved" function. Third, there are several other pins that also have unused codepoints in their function settings, e.g., PIO0_3 or PIO0_4/SCL but there's no "R" in evidence there. So that "R" doesnt seem to make any sense, may cause confusion, and makes the symbol more crowded.
48 lines
1.9 KiB
Plaintext
48 lines
1.9 KiB
Plaintext
EESchema-LIBRARY Version 2.3 Date: Thu Dec 20 19:44:55 2012
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#encoding utf-8
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#
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# LPC1100-QFN33
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#
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DEF LPC1100-QFN33 U 0 40 Y Y 1 F N
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F0 "U" -1500 1400 60 H V L CNN
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F1 "LPC1100-QFN33" 1050 -1300 60 H V L CNN
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DRAW
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S -1500 1300 1700 -1200 0 1 0 N
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X PIO2_0/nDTR 1 -1800 450 300 R 50 50 1 1 T
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X nRESET/PIO0_0 2 -1800 300 300 R 50 50 1 1 T
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X PIO0_1/CLKOUT/CT32B0_MAT2 3 -1800 150 300 R 50 50 1 1 T
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X XTALIN 4 -1800 0 300 R 50 50 1 1 I
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X XTALOUT 5 -1800 -150 300 R 50 50 1 1 O
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X VDD 6 -1800 -300 300 R 50 50 1 1 W
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X PIO1_8/CT16B1_CAP0 7 -1800 -450 300 R 50 50 1 1 T
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X PIO0_2/SSEL0/CT16B0_CAP0 8 -1800 -600 300 R 50 50 1 1 T
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X PIO0_3 9 -600 -1500 300 U 50 50 1 1 T
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X PIO0_4/SCL 10 -450 -1500 300 U 50 50 1 1 T
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X PIO1_10/AD6/CT16B1_MAT1 20 2000 -150 300 L 50 50 1 1 T
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X PIO1_5/nRTS/CT32B0_CAP0 30 -300 1600 300 D 50 50 1 1 T
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X PIO0_5/SDA 11 -300 -1500 300 U 50 50 1 1 T
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X PIO0_11/AD0/CT32B0_MAT3 21 2000 0 300 L 50 50 1 1 T
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X PIO1_6/RXD/CT32B0_MAT0 31 -450 1600 300 D 50 50 1 1 T
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X PIO1_9/CT16B1_MAT0 12 -150 -1500 300 U 50 50 1 1 T
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X PIO1_0/AD1/CT32B1_CAP0 22 2000 150 300 L 50 50 1 1 T
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X PIO1_7/TXD/CT32B0_MAT1 32 -600 1600 300 D 50 50 1 1 T
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X PIO3_4 13 0 -1500 300 U 50 50 1 1 T
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X PIO1_1/AD2/CT32B1_MAT0 23 2000 300 300 L 50 50 1 1 T
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X VSS 33 900 -1500 300 U 50 50 1 1 W
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X PIO3_5 14 150 -1500 300 U 50 50 1 1 T
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X PIO1_2/AD3/CT32B1_MAT1 24 2000 450 300 L 50 50 1 1 T
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X PIO0_6/SCK0 15 300 -1500 300 U 50 50 1 1 T
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X SWDIO/PIO1_3/AD4/CT32B1_MAT2 25 450 1600 300 D 50 50 1 1 T
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X PIO0_7/nCTS 16 450 -1500 300 U 50 50 1 1 T
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X PIO1_4/AD5/CT32B1_MAT3/WAKEUP 26 300 1600 300 D 50 50 1 1 T
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X PIO0_8/MISO0/CT16B0_MAT0 17 2000 -600 300 L 50 50 1 1 T
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X PIO1_11/AD7 27 150 1600 300 D 50 50 1 1 T
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X PIO0_9/MOSI0/CT16B0_MAT1 18 2000 -450 300 L 50 50 1 1 T
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X PIO3_2 28 0 1600 300 D 50 50 1 1 T
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X SWCLK/PIO0_10/SCK0/CT16B0_MAT2 19 2000 -300 300 L 50 50 1 1 T
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X VDD 29 -150 1600 300 D 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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#End Library
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