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13 lines
189 B
C
13 lines
189 B
C
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/*
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* SIE FPGA init
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*
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*/
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#include "jz47xx_gpio.h"
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#include "jz47xx_mmap.h"
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#define CS2_PORT JZ_GPIO_PORT_B
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#define CS2_PIN 26
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JZ_REG * jz_cs2_init();
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