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git://projects.qi-hardware.com/nn-usb-fpga.git
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72 lines
2.1 KiB
VHDL
72 lines
2.1 KiB
VHDL
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---------------------------------------------------------------------
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-- TITLE: Program Counter Next
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/8/01
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-- FILENAME: pc_next.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Implements the Program Counter logic.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity pc_next is
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port(clk : in std_logic;
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reset_in : in std_logic;
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_future : out std_logic_vector(31 downto 2);
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pc_current : out std_logic_vector(31 downto 2);
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pc_plus4 : out std_logic_vector(31 downto 2));
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end; --pc_next
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architecture logic of pc_next is
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signal pc_reg : std_logic_vector(31 downto 2);
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begin
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pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
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opcode25_0, pc_source, pc_reg)
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variable pc_inc : std_logic_vector(31 downto 2);
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variable pc_next : std_logic_vector(31 downto 2);
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begin
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pc_inc := bv_increment(pc_reg); --pc_reg+1
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case pc_source is
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when FROM_INC4 =>
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pc_next := pc_inc;
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when FROM_OPCODE25_0 =>
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pc_next := pc_reg(31 downto 28) & opcode25_0;
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when FROM_BRANCH | FROM_LBRANCH =>
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if take_branch = '1' then
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pc_next := pc_new;
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else
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pc_next := pc_inc;
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end if;
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when others =>
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pc_next := pc_inc;
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end case;
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if pause_in = '1' then
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pc_next := pc_reg;
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end if;
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if reset_in = '1' then
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pc_reg <= ZERO(31 downto 2);
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pc_next := pc_reg;
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elsif rising_edge(clk) then
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pc_reg <= pc_next;
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end if;
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pc_future <= pc_next;
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pc_current <= pc_reg;
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pc_plus4 <= pc_inc;
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end process;
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end; --logic
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