nn-usb-fpga/Examples/sram/logic/simulation/sram_bus_TIMING_TB.do

vlib work
vlog   -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB glbl
view wave
#do wave.do
add wave *
view structure
view signals
run 5us
Adding post route simulation to FPGA examples 2010-05-10 22:56:51 +03:00			`vlib work`
			`vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"`
Adding iverilog simulation support 2010-05-12 17:36:30 +03:00			`vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl`
Adding post route simulation to FPGA examples 2010-05-10 22:56:51 +03:00			`view wave`
			`#do wave.do`
			`add wave *`
			`view structure`
			`view signals`
			`run 5us`