nn-usb-fpga/Software/xc3sprog/byte-order.txt

The IO routines that shift data out to the JTAG port start with the first byte of the buffer given. Each byte is is output LSB first. If the byte order was the same as the SVF file then the entire buffer would have to be stored and then reversed, causing problems for embedded JTAG servers with limited memory. 


The table below shows an example of the byte order reversal required for playing an SVF file.

SVF	IO buffer
..	ff
..	aa
..	33
..	00
00	..
33	..
aa	..
ff	..


For a Xilinx bit file, which is MSB first, each byte is bit-reversed as shown below.

BIT	IO buffer
ff	ff
55	aa
cc	33
00	00
..	..
..	..
..	..
..	..
Adding Xc3sprog ported to SAKC Adding FPGA sram hdl code and user space code Fixing some errors: LCD's pinout connector is swapped FPGA TDI SIGNAL must be routed to another pin (C14), right now is DQMH Remove R11 Check JZ4725 symbol's component (PORTD is wrong) Adding PB2 and PB3 wiring ADC's vref to external connector Adding power LED Adding CPU Led 2010-03-17 22:42:11 +02:00			`The IO routines that shift data out to the JTAG port start with the first byte of the buffer given. Each byte is is output LSB first. If the byte order was the same as the SVF file then the entire buffer would have to be stored and then reversed, causing problems for embedded JTAG servers with limited memory.`



			`The table below shows an example of the byte order reversal required for playing an SVF file.`

			`SVF IO buffer`
			`.. ff`
			`.. aa`
			`.. 33`
			`.. 00`
			`00 ..`
			`33 ..`
			`aa ..`
			`ff ..`



			`For a Xilinx bit file, which is MSB first, each byte is bit-reversed as shown below.`

			`BIT IO buffer`
			`ff ff`
			`55 aa`
			`cc 33`
			`00 00`
			`.. ..`
			`.. ..`
			`.. ..`
			`.. ..`