nn-usb-fpga/Examples/ehw4/logic/ehw.v

`timescale 1ns / 1ps
module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led, 
                irq_pin);
  
    parameter   B = (7);

    input       clk, addr, nwe, ncs, noe, reset;
    inout [B:0] sram_data;
    output      led;
    output      irq_pin;

    // synchronize signals                               
    reg    	    sncs, snwe;
    reg     [12:0]  buffer_addr; 
    reg     [B:0]   buffer_data;   

    // bram-cpu interfaz
    reg             we;
    reg             w_st=0;
    reg     [B:0]   wdBus;
    wire    [B:0]   rdBus;
    wire    [12:0]  addr;
    reg     [7:0]   bae;


    // bram-evalfit interfaz
    wire    we_eval, en_ev; 
    wire    [63:0] ev_do;
    wire    [63:0] ev_di;

    // Interconnection
    wire   [31:0] mt_rnd;
    wire   [31:0] reg0;
    wire   [31:0] reg1;
    wire   [31:0] reg2;
    wire   [31:0] reg3;
    wire   [31:0] reg4;
    wire   [7:0]  status;
    wire   [15:0] error;
    wire   [8:0]  evalfit_addr;

    wire   en_fit;
    wire   [15:0] max_com;
    wire   [3:0]  max_lev;
    wire   [7:0]  control;

     // Test : LED blinking
    reg     [25:0]  counter;
    always @(posedge clk) begin
        if (~reset)
            counter <= {25{1'b0}};
        else
            counter <= counter + 1;
    end 
    assign led = counter[24];
    
    // Data Bus direction control
    wire   T = ~noe | ncs;
    assign sram_data = T?8'bZ:rdBus;

    // synchronize assignment
    always  @(negedge clk)
    begin
        sncs   <= ncs;
        snwe   <= nwe;
        buffer_data <= sram_data;
        buffer_addr <= addr;
    end

    // write access cpu to bram
    always @(posedge clk)
    if(~reset) {w_st, we, wdBus} <= 0;
      else begin
        wdBus <= buffer_data;
        case (w_st)
          0: begin
              we <= 0;
              if(sncs | snwe) w_st <= 1;
          end
          1: begin
            if(~(sncs | snwe)) begin
              we    <= 1;
              w_st  <= 0;
            end	
            else we <= 0;
          end
        endcase
      end


 // Address Decoder
 // We have 2 memory blocks 1: 512 x 64 bits memory 32kb = 4kB  0000 - 0FFF  buffer_addr[12] = 0
 //                         2: Register Bank                    1000 - 101F  buffer_addr[12] = 1

 // SIE has an eight bits data bus, this module generate the required signals to create a 64 bits word.
  always @(buffer_addr)
   begin
     if(~buffer_addr[12]) begin
        case (buffer_addr[2:0])
          0: bae <= 8'h01;
          1: bae <= 8'h02;
          2: bae <= 8'h04;
          3: bae <= 8'h08;
          4: bae <= 8'h10;
          5: bae <= 8'h20;
          6: bae <= 8'h40;
          7: bae <= 8'h80;
        endcase
     end
     else
       bae <= 8'h00;
   end


 // Memories

RAMB16_S4_S4 ba0( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[3:0]), .DOB(ev_di[3:0]));  //D3-D0
RAMB16_S4_S4 ba1( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[7:4]), .DOB(ev_di[7:4]));  //D7-D4 

RAMB16_S4_S4 ba2( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[11:8]),  .DOB(ev_di[11:8])); //D11-D8
RAMB16_S4_S4 ba3( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[15:12]), .DOB(ev_di[15:12]));//D15-D12 

RAMB16_S4_S4 ba4( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[19:16]), .DOB(ev_di[19:16])); //D19-D16
RAMB16_S4_S4 ba5( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[23:20]), .DOB(ev_di[23:20])); //D23-D20 

RAMB16_S4_S4 ba6( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[27:24]), .DOB(ev_di[27:24])); //D27-D24
RAMB16_S4_S4 ba7( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[31:28]), .DOB(ev_di[31:28])); //D31-D28

RAMB16_S4_S4 ba8( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[35:32]), .DOB(ev_di[35:32])); //D35-D32
RAMB16_S4_S4 ba9( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[39:36]), .DOB(ev_di[39:36])); //D39-D36

RAMB16_S4_S4 ba10(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[43:40]), .DOB(ev_di[43:40])); //D43-D40
RAMB16_S4_S4 ba11(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[47:44]), .DOB(ev_di[47:44])); //D47-D44

RAMB16_S4_S4 ba12(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[51:48]), .DOB(ev_di[51:48])); //D51-D48
RAMB16_S4_S4 ba13(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[55:52]), .DOB(ev_di[55:52])); //D55-D52

RAMB16_S4_S4 ba14(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[3:0]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[59:56]), .DOB(ev_di[59:56])); //D59-D56
RAMB16_S4_S4 ba15(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we),     .DIA(wdBus[7:4]),
                  .CLKB(~clk), .ENB(en_ev),  .SSRB(1'b0), .ADDRB(evalfit_addr),      .WEB(we_eval),.DIB(ev_do[63:60]), .DOB(ev_di[63:60])); //D63-D60

 // evalfit_peripheral
evalfit_peripheral evalfit( .clk(clk), .reset(reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
                            .peripheral_mem_in(ev_di), .peripheral_mem_en(en_eval), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval), 
                            .peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status), .errores(error), 
                            .fin_ack(irq_pin), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));

reg_bank RegBank( .clk(clk), .reset(reset), .en(buffer_addr[12]), .we(we), .wdBus(wdBus), .rdBus(rdBus), .address(buffer_addr[4:0]), 
                  .reg0(reg0), .reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4), .error(error), .status(status),
                  .max_com(max_com), .max_lev(max_lev), .control(control));

// mt_mem
 mt_mem random( .clk(clk), .ena(1'b1), .resetn(~reset), .random(mt_rnd));

	       
endmodule