2010-05-10 22:56:51 +03:00
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m255
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13
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cModel Technology
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d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
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vglbl
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IT?5S;>bN`@zG_25]R_4A33
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VnN]4Gon>inod6>M^M2[SV1
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w1273510321
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Fglbl.v
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L0 5
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OE;L;6.0d;29
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r1
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31
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2010-05-12 18:06:23 +03:00
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o+libext+.v
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2010-05-10 22:56:51 +03:00
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vsram_bus
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2010-05-12 18:06:23 +03:00
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I4L5C3LJ<U_bBN0U__mYo>0
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V7R>S0^PdJz?6eY;E[l1^E2
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w1273543761
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F../sram_bus.v
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L0 2
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2010-05-10 22:56:51 +03:00
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OE;L;6.0d;29
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r1
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31
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2010-05-12 18:06:23 +03:00
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o+libext+.v
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2010-05-12 17:36:30 +03:00
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vsram_bus_TB
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IeNSImUgW[X4l`QoUVUKI`3
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V<VFiY^801Z<UUJ?^z?JM20
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2010-05-12 18:06:23 +03:00
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w1273676679
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2010-05-12 17:36:30 +03:00
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F../sram_bus_TB.v
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L0 3
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OE;L;6.0d;29
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r1
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31
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2010-05-12 18:06:23 +03:00
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o+libext+.v
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2010-05-12 17:36:30 +03:00
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nsram_bus_@t@b
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2010-05-10 22:56:51 +03:00
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vsram_bus_TB_v
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IA=m;kT@<eh:`ekMlOPXX@0
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VQ[@Nfjd=de;Dc[[gj0bf41
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2010-05-12 17:36:30 +03:00
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w1273541944
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2010-05-10 22:56:51 +03:00
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F../sram_bus_TB.v
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L0 3
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OE;L;6.0d;29
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r1
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31
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2010-05-12 17:36:30 +03:00
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o+libext+.v
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2010-05-10 22:56:51 +03:00
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nsram_bus_@t@b_v
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