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66 lines
3.0 KiB
VHDL
66 lines
3.0 KiB
VHDL
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---------------------------------------------------------------------
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-- TITLE: Shifter Unit
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- Matthias Gruenewald
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-- DATE CREATED: 2/2/01
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-- FILENAME: shifter.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Implements the 32-bit shifter unit.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity shifter is
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generic(shifter_type : string := "DEFAULT");
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port(value : in std_logic_vector(31 downto 0);
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shift_amount : in std_logic_vector(4 downto 0);
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shift_func : in shift_function_type;
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c_shift : out std_logic_vector(31 downto 0));
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end; --entity shifter
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architecture logic of shifter is
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-- type shift_function_type is (
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-- shift_nothing, shift_left_unsigned,
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-- shift_right_signed, shift_right_unsigned);
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signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
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signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
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signal fills : std_logic_vector(31 downto 16);
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begin
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fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
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and value(31) = '1'
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else "0000000000000000";
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shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
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shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
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shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
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shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
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shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
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shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
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shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
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shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
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shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
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shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
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GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
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c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
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shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
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shift_func = SHIFT_RIGHT_SIGNED else
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ZERO;
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end generate;
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AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
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c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
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c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
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shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
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c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
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end generate;
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end; --architecture logic
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