nn-usb-fpga/plasma/logic/plasma_TB.v

`timescale 1ns / 1ps

module plasma_TB_v;

   reg clk;
   reg reset;


   plasma uut( .clk(clk), .reset(reset));


   parameter PERIOD  = 20;
   parameter real DUTY_CYCLE = 0.5;
   parameter OFFSET  = 0;
   parameter TSET    = 3;
   parameter THLD    = 3;
   parameter NWS     = 3;
   parameter CAM_OFF = 4000;
	 
	 reg [15:0] data_tx;	 


	event reset_trigger;
	event reset_done_trigger;

    initial begin // Reset the system, Start the image capture process
      forever begin 
        @ (reset_trigger);
        @ (negedge clk);
        reset = 1;
        @ (negedge clk);
        reset = 0;
        -> reset_done_trigger;
      end
    end

	 
    initial begin  // Initialize Inputs
      clk = 0;
    end

   initial  begin  // Process for clk
     #OFFSET;
     forever
     begin
       clk = 1'b0;
       #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
       #(PERIOD*DUTY_CYCLE);
     end
   end

 initial begin: TEST_CASE	
     #10 -> reset_trigger;
     @ (reset_done_trigger); 
     // Write data to SRAM
 end
endmodule