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Fixing plasma files.. Now works :)

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This commit is contained in:
Carlos Camargo
2010-05-27 21:26:56 -05:00
parent 61d4408f2a
commit 01e672d028
15 changed files with 421 additions and 875 deletions
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3
Examples/sram/logic/Makefile
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@@ -89,8 +89,7 @@ timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
iversim:
$(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
# $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
$(IVERILOG) -Wall -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
gtkwave simulation/$(DESIGN)_TB.vcd&