Adding simulation files to blink example

Examples/blink/logic/Makefile

@@ -4,9 +4,8 @@ DEVICE          = xc3s250e-VQ100-4
 BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
                   -g CRC:enable -g StartUpClk:CCLK
 
-SIM_CMD         = /opt/cad/modeltech/bin/vsim 
+SIM_CMD         = vsim 
 SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
-#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
 SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
 SAKC_IP         = 192.168.254.101
 
@@ -18,13 +17,10 @@ remake:         clean-build all
 
 clean:
 	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
-	rm *.bit
+	rm -f *.bit
 
-clean-build: clean
-	rm -rf build
-
-cleanall:   clean
-	rm -rf build $(DESIGN).bit
+cleanall: clean
+	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf
 
 bits:           $(DESIGN).bit
 

Examples/blink/logic/blink.v

@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 module blink(clk, reset, led);
-  parameter     B = (7);
-
   input            clk, reset;
   output           led;
 

Examples/blink/logic/blink_TB.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+
+module blink_TB_v;
+
+   reg  clk;
+   reg  reset;
+   wire led;
+
+   blink uut ( .clk(clk), .reset(reset), .led(led));
+
+   parameter PERIOD          = 20;
+   parameter real DUTY_CYCLE = 0.5;
+   parameter OFFSET          = 0;
+   parameter TSET            = 3;
+   parameter THLD            = 3;
+   parameter NWS             = 3;
+	 
+   event reset_trigger;
+
+
+   initial begin  // Initialize Inputs
+      clk = 0; reset = 0;
+   end
+
+   initial  begin  // Process for clk
+     #OFFSET;
+     forever
+       begin
+         clk = 1'b0;
+         #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
+         #(PERIOD*DUTY_CYCLE);
+       end
+   end
+
+   initial begin // Reset the system, Start the image capture process
+      forever begin 
+        @ (reset_trigger);
+        @ (negedge clk);
+        reset = 1;
+        @ (negedge clk);
+        reset = 0;
+      end
+   end
+	 
+
+   initial begin: TEST_CASE	
+     #10 -> reset_trigger;
+   end
+
+endmodule
+

Examples/blink/logic/simulation/blink_TB.do

@@ -0,0 +1,12 @@
+vlib work
+vlog  +acc  "../blink.v"
+vlog  +acc  "../blink_TB.v"
+vlog  +acc  "/opt/cad/Xilinx/verilog/src/glbl.v"
+vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver  blink_TB_v glbl
+view wave
+do wave.do
+#add wave *
+add wave /glbl/GSR
+view structure
+view signals
+run 15ms

Examples/blink/logic/simulation/wave.do

@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /blink_TB_v/clk
+add wave -noupdate -format Logic /blink_TB_v/reset
+add wave -noupdate -format Logic /blink_TB_v/led
+add wave -noupdate -format Event /blink_TB_v/reset_trigger
+add wave -noupdate -format Logic /glbl/GSR
+add wave -noupdate -format Literal -radix hexadecimal /blink_TB_v/uut/counter
+add wave -noupdate -format Logic /glbl/GSR
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {17827 ps} 0}
+configure wave -namecolwidth 218
+configure wave -valuecolwidth 40
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {240328 ps}