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Adding iverilog simulation support

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This commit is contained in:
Carlos Camargo
2010-05-12 09:36:30 -05:00
parent 23184f39dd
commit 079d8042f6
15 changed files with 72 additions and 30 deletions
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2
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do
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@@ -1,6 +1,6 @@
vlib work
vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
view wave
#do wave.do
add wave *