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Adding iverilog simulation support

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This commit is contained in:
Carlos Camargo
2010-05-12 09:36:30 -05:00
parent 23184f39dd
commit 079d8042f6
15 changed files with 72 additions and 30 deletions
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20
Examples/sram/logic/simulation/transcript
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@@ -13,15 +13,15 @@
# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
# -- Compiling module sram_bus
# -- Compiling module glbl
# -- Compiling module sram_bus_TB_v
# -- Compiling module sram_bus_TB
# ** Warning: glbl.v(5): 'glbl' already exists.
# -- Compiling module glbl
#
# Top level modules:
# glbl
# sram_bus_TB_v
# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl
# Loading work.sram_bus_TB_v
# sram_bus_TB
# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
# Loading work.sram_bus_TB
# Loading work.sram_bus
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
@@ -33,7 +33,6 @@
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
@@ -43,9 +42,9 @@
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
# Loading work.glbl
# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
# Region: /sram_bus_TB_v/uut
# Region: /sram_bus_TB/uut
# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
# Region: /sram_bus_TB_v/uut
# Region: /sram_bus_TB/uut
# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
@@ -55,9 +54,4 @@
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
exit
quit