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Adding ghdl simulation to plasma project

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This commit is contained in:
Carlos Camargo
2010-08-12 19:51:53 -05:00
parent 18e79c4816
commit 1254422744
8 changed files with 136 additions and 136 deletions
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50
plasma/logic/Makefile
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@@ -1,13 +1,26 @@
DESIGN = plasma
PINS = $(DESIGN).ucf
DEVICE = xc3s500e-VQ100-4
#DEVICE = xc3s500e-fg320-4
BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
-g CRC:enable -g StartUpClk:CCLK
SIM_CMD = /opt/cad/modeltech/bin/vsim
SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SIMTOP = $(DESIGN)_tb
GHDL_SIM_OPT = --stop-time=1ms
SIMDIR = simu
GHDL_CMD = ghdl
GHDL_SIMU_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
GHDL_SYNTHESIS_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
GHDL_PANDR_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/simprim --warn-no-vital-generic
VIEW_CMD = gtkwave
TESTBENCH_FILE = $(DESIGN)_TB.vhd
SYNT_TESTBENCH_FILE = $(DESIGN)_TB_syn.vhd
SYNTHESIS_FILE = simu/$(DESIGN)_synt.vhd
LIBRARY_FILE = mlite_pack.vhd
SRC_HDL = mlite_pack.vhd plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd pipeline.vhd reg_bank.vhd uart.vhd
all: bits
@@ -22,7 +35,7 @@ clean:
clean-build:
rm -rf build
cleanall: clean
cleanall: clean clean_ghdl
rm -rf build work $(DESIGN).bit
bits: $(DESIGN).bit
@@ -67,15 +80,36 @@ $(DESIGN).bit: build/project_r.ncd build/project_r.twr
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
@mv -f build/project_r.bit $@
build/project_r.v: build/project_r.ncd
cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
build/project.vhd: build/project.ngc
cd build && netgen -w -ofmt vhdl project.ngc project.vhd
sim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
ghdl-simu : ghdl-compil ghdl-run ghdl-view
sim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
ghdl-synthesis : ghdl-compil-synthesis ghdl-run ghdl-view
ghdl-compil :
mkdir -p simu
$(GHDL_CMD) -i $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(SRC_HDL)
$(GHDL_CMD) -m $(GHDL_SIMU_FLAGS) -fexplicit --workdir=simu --work=work $(SIMTOP)
@mv $(SIMTOP) simu/$(SIMTOP)
ghdl-compil-synthesis: build/project.vhd
mkdir -p simu
cp build/project.vhd simu/$(DESIGN)_synt.vhd
$(GHDL_CMD) -i $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SYNT_TESTBENCH_FILE) $(SYNTHESIS_FILE)
$(GHDL_CMD) -m $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SIMTOP)
@mv $(SIMTOP) simu/$(SIMTOP)
ghdl-run :
@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
ghdl-view:
gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
clean_ghdl :
$(GHDL_CMD) --clean --workdir=simu
-rm -rf simu