mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Adding evolvable hardware example
This commit is contained in:
Carlos Camargo
@@ -30,6 +30,7 @@ image.lst: image
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image.bin: image
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$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.bin
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$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image_bin.bin
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image.srec: image image.lst
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$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
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@@ -1,454 +0,0 @@
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image: file format elf32-lm32
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .text 00000270 00000000 00000000 00000054 2**2
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CONTENTS, ALLOC, LOAD, CODE
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1 .rodata 0000001c 00000270 00000270 000002c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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2 .data 0000000c 0000028c 0000028c 000002e0 2**2
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CONTENTS, ALLOC, LOAD, DATA
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3 .bss 00000004 00000298 00000298 000002ec 2**2
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ALLOC
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4 .debug_abbrev 00000219 00000000 00000000 000002ec 2**0
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CONTENTS, READONLY, DEBUGGING
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5 .debug_info 000003d0 00000000 00000000 00000505 2**0
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CONTENTS, READONLY, DEBUGGING
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6 .debug_line 000002d8 00000000 00000000 000008d5 2**0
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CONTENTS, READONLY, DEBUGGING
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7 .debug_frame 000000a0 00000000 00000000 00000bb0 2**2
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CONTENTS, READONLY, DEBUGGING
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8 .debug_loc 000000fb 00000000 00000000 00000c50 2**0
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CONTENTS, READONLY, DEBUGGING
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9 .debug_pubnames 000000bc 00000000 00000000 00000d4b 2**0
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CONTENTS, READONLY, DEBUGGING
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10 .debug_aranges 00000040 00000000 00000000 00000e07 2**0
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CONTENTS, READONLY, DEBUGGING
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11 .debug_ranges 00000018 00000000 00000000 00000e47 2**0
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CONTENTS, READONLY, DEBUGGING
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12 .debug_str 0000017b 00000000 00000000 00000e5f 2**0
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CONTENTS, READONLY, DEBUGGING
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13 .comment 00000011 00000000 00000000 00000fda 2**0
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CONTENTS, READONLY
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Disassembly of section .text:
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00000000 <_ftext>:
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0: 98 00 00 00 xor r0,r0,r0
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4: d0 00 00 00 wcsr IE,r0
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8: 78 01 00 00 mvhi r1,0x0
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c: 38 21 00 00 ori r1,r1,0x0
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10: d0 e1 00 00 wcsr EBA,r1
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14: f8 00 00 03 calli 20 <_crt0>
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18: 34 00 00 00 nop
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1c: 34 00 00 00 nop
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00000020 <_crt0>:
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20: 78 1c 00 00 mvhi sp,0x0
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24: 3b 9c 0f fc ori sp,sp,0xffc
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28: 78 1a 00 00 mvhi gp,0x0
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2c: 3b 5a 02 a0 ori gp,gp,0x2a0
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30: 78 01 00 00 mvhi r1,0x0
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34: 38 21 02 98 ori r1,r1,0x298
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38: 78 03 00 00 mvhi r3,0x0
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3c: 38 63 02 9c ori r3,r3,0x29c
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00000040 <.clearBSS>:
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40: 44 23 00 04 be r1,r3,50 <.callMain>
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44: 58 20 00 00 sw (r1+0),r0
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48: 34 21 00 04 addi r1,r1,4
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4c: e3 ff ff fd bi 40 <.clearBSS>
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00000050 <.callMain>:
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50: 34 01 00 00 mvi r1,0
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54: 34 02 00 00 mvi r2,0
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58: 34 03 00 00 mvi r3,0
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5c: f8 00 00 1d calli d0 <main>
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00000060 <irq_enable>:
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60: 34 01 00 01 mvi r1,1
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64: d0 01 00 00 wcsr IE,r1
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68: c3 a0 00 00 ret
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0000006c <irq_mask>:
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6c: 34 01 00 0f mvi r1,15
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70: d0 21 00 00 wcsr IM,r1
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74: c3 a0 00 00 ret
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00000078 <irq_disable>:
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78: 34 01 00 00 mvi r1,0
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7c: d0 01 00 00 wcsr IE,r1
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80: c3 a0 00 00 ret
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00000084 <jump>:
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84: c0 20 00 00 b r1
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00000088 <halt>:
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88: e0 00 00 00 bi 88 <halt>
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0000008c <read_uint32>:
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*/
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#include "soc-hw.h"
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/* prototypes */
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uint32_t read_uint32()
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{
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8c: 37 9c ff f8 addi sp,sp,-8
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90: 5b 8b 00 08 sw (sp+8),r11
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94: 5b 9d 00 04 sw (sp+4),ra
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uint32_t val = 0, i;
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for (i = 0; i < 4; i++) {
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val <<= 8;
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val += (uint8_t)uart_getchar();
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98: f8 00 00 57 calli 1f4 <uart_getchar>
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uint32_t read_uint32()
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{
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uint32_t val = 0, i;
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for (i = 0; i < 4; i++) {
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val <<= 8;
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9c: 3c 2b 00 08 sli r11,r1,8
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val += (uint8_t)uart_getchar();
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a0: f8 00 00 55 calli 1f4 <uart_getchar>
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a4: b5 61 08 00 add r1,r11,r1
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uint32_t read_uint32()
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{
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uint32_t val = 0, i;
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for (i = 0; i < 4; i++) {
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val <<= 8;
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a8: 3c 2b 00 08 sli r11,r1,8
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val += (uint8_t)uart_getchar();
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ac: f8 00 00 52 calli 1f4 <uart_getchar>
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b0: b5 61 08 00 add r1,r11,r1
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uint32_t read_uint32()
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{
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uint32_t val = 0, i;
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for (i = 0; i < 4; i++) {
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val <<= 8;
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b4: 3c 2b 00 08 sli r11,r1,8
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val += (uint8_t)uart_getchar();
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b8: f8 00 00 4f calli 1f4 <uart_getchar>
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}
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return val;
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}
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bc: b5 61 08 00 add r1,r11,r1
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c0: 2b 9d 00 04 lw ra,(sp+4)
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c4: 2b 8b 00 08 lw r11,(sp+8)
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c8: 37 9c 00 08 addi sp,sp,8
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cc: c3 a0 00 00 ret
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000000d0 <main>:
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int main(int argc, char **argv)
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{
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d0: 37 9c ff e4 addi sp,sp,-28
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d4: 5b 8b 00 1c sw (sp+28),r11
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d8: 5b 8c 00 18 sw (sp+24),r12
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dc: 5b 8d 00 14 sw (sp+20),r13
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e0: 5b 8e 00 10 sw (sp+16),r14
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e4: 5b 8f 00 0c sw (sp+12),r15
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e8: 5b 90 00 08 sw (sp+8),r16
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ec: 5b 9d 00 04 sw (sp+4),ra
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int8_t *p;
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uint8_t c;
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// Initialize UART
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uart_init();
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f0: f8 00 00 40 calli 1f0 <uart_init>
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c = '*'; // print msg on first iteration
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for(;;) {
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uint32_t start, size;
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switch (c) {
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f4: 34 0d 00 67 mvi r13,103
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{
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int8_t *p;
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uint8_t c;
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// Initialize UART
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uart_init();
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f8: 34 01 00 2a mvi r1,42
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c = '*'; // print msg on first iteration
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for(;;) {
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uint32_t start, size;
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switch (c) {
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fc: 34 0e 00 75 mvi r14,117
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100: 34 0f 00 64 mvi r15,100
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case 'g': // goto
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start = read_uint32();
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jump(start);
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break;
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default:
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uart_putstr("**SAKC/bootloader** > \r\n");
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104: 78 10 00 00 mvhi r16,0x0
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c = '*'; // print msg on first iteration
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for(;;) {
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uint32_t start, size;
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switch (c) {
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108: 44 2d 00 08 be r1,r13,128 <main+0x58>
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10c: 44 2e 00 16 be r1,r14,164 <main+0x94>
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110: 44 2f 00 0a be r1,r15,138 <main+0x68>
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case 'g': // goto
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start = read_uint32();
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jump(start);
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break;
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default:
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uart_putstr("**SAKC/bootloader** > \r\n");
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114: ba 00 08 00 mv r1,r16
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118: 38 21 02 70 ori r1,r1,0x270
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11c: f8 00 00 48 calli 23c <uart_putstr>
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break;
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};
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c = uart_getchar();
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120: f8 00 00 35 calli 1f4 <uart_getchar>
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c = '*'; // print msg on first iteration
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for(;;) {
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uint32_t start, size;
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switch (c) {
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124: 5c 2d ff fa bne r1,r13,10c <main+0x3c>
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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uart_putchar( *p );
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break;
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case 'g': // goto
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start = read_uint32();
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128: fb ff ff d9 calli 8c <read_uint32>
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jump(start);
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12c: fb ff ff d6 calli 84 <jump>
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break;
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default:
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uart_putstr("**SAKC/bootloader** > \r\n");
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break;
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};
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c = uart_getchar();
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130: f8 00 00 31 calli 1f4 <uart_getchar>
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134: e3 ff ff fc bi 124 <main+0x54>
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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*p = uart_getchar();
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break;
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case 'd': // download
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start = read_uint32();
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138: fb ff ff d5 calli 8c <read_uint32>
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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13c: b8 20 58 00 mv r11,r1
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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*p = uart_getchar();
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break;
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case 'd': // download
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start = read_uint32();
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size = read_uint32();
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140: fb ff ff d3 calli 8c <read_uint32>
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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144: b5 61 60 00 add r12,r11,r1
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148: 51 6c ff f6 bgeu r11,r12,120 <main+0x50>
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uart_putchar( *p );
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14c: 41 61 00 00 lbu r1,(r11+0)
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*p = uart_getchar();
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break;
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case 'd': // download
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start = read_uint32();
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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150: 35 6b 00 01 addi r11,r11,1
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uart_putchar( *p );
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154: f8 00 00 31 calli 218 <uart_putchar>
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*p = uart_getchar();
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break;
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case 'd': // download
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start = read_uint32();
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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158: 55 8b ff fd bgu r12,r11,14c <main+0x7c>
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break;
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default:
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uart_putstr("**SAKC/bootloader** > \r\n");
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break;
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};
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c = uart_getchar();
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15c: f8 00 00 26 calli 1f4 <uart_getchar>
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160: e3 ff ff f1 bi 124 <main+0x54>
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for(;;) {
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uint32_t start, size;
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switch (c) {
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case 'u': // upload
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start = read_uint32();
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164: fb ff ff ca calli 8c <read_uint32>
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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168: b8 20 58 00 mv r11,r1
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uint32_t start, size;
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switch (c) {
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case 'u': // upload
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start = read_uint32();
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size = read_uint32();
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16c: fb ff ff c8 calli 8c <read_uint32>
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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170: b5 61 60 00 add r12,r11,r1
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174: 51 6c ff eb bgeu r11,r12,120 <main+0x50>
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*p = uart_getchar();
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178: f8 00 00 1f calli 1f4 <uart_getchar>
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17c: 31 61 00 00 sb (r11+0),r1
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switch (c) {
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case 'u': // upload
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start = read_uint32();
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size = read_uint32();
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for (p = (int8_t *) start; p < (int8_t *) (start+size); p++)
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180: 35 6b 00 01 addi r11,r11,1
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184: 55 8b ff fd bgu r12,r11,178 <main+0xa8>
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break;
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default:
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uart_putstr("**SAKC/bootloader** > \r\n");
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break;
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};
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c = uart_getchar();
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188: f8 00 00 1b calli 1f4 <uart_getchar>
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18c: e3 ff ff e6 bi 124 <main+0x54>
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00000190 <sleep>:
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void sleep(int msec)
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{
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uint32_t tcr;
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// Use timer0.1
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timer0->compare1 = (FCPU/1000)*msec;
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190: 78 02 00 00 mvhi r2,0x0
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194: 38 42 02 90 ori r2,r2,0x290
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198: 38 03 c3 50 mvu r3,0xc350
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19c: 28 42 00 00 lw r2,(r2+0)
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1a0: 88 23 08 00 mul r1,r1,r3
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1a4: 58 41 00 10 sw (r2+16),r1
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timer0->counter1 = 0;
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1a8: 34 01 00 00 mvi r1,0
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1ac: 58 41 00 14 sw (r2+20),r1
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timer0->tcr1 = TIMER_EN | TIMER_IRQEN;
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1b0: 34 01 00 0a mvi r1,10
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1b4: 58 41 00 0c sw (r2+12),r1
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do {
|
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//halt();
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tcr = timer0->tcr1;
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1b8: 28 41 00 0c lw r1,(r2+12)
|
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} while ( ! (tcr & TIMER_TRIG) );
|
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1bc: 20 21 00 01 andi r1,r1,0x1
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1c0: 44 20 ff fe be r1,r0,1b8 <sleep+0x28>
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}
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1c4: c3 a0 00 00 ret
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000001c8 <tic_init>:
|
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|
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void tic_init()
|
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{
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// Setup timer0.0
|
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timer0->compare0 = (FCPU/1000);
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1c8: 78 01 00 00 mvhi r1,0x0
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||||
1cc: 38 21 02 90 ori r1,r1,0x290
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||||
1d0: 28 21 00 00 lw r1,(r1+0)
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1d4: 38 02 c3 50 mvu r2,0xc350
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1d8: 58 22 00 04 sw (r1+4),r2
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||||
timer0->counter0 = 0;
|
||||
1dc: 34 02 00 00 mvi r2,0
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||||
1e0: 58 22 00 08 sw (r1+8),r2
|
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timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
|
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1e4: 34 02 00 0e mvi r2,14
|
||||
1e8: 58 22 00 00 sw (r1+0),r2
|
||||
}
|
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1ec: c3 a0 00 00 ret
|
||||
|
||||
000001f0 <uart_init>:
|
||||
//uart0->lcr = 0x03; // Line Control Register: 8N1
|
||||
//uart0->mcr = 0x00; // Modem Control Register
|
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|
||||
// Setup Divisor register (Fclk / Baud)
|
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//uart0->div = (FCPU/(57600*16));
|
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}
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1f0: c3 a0 00 00 ret
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||||
|
||||
000001f4 <uart_getchar>:
|
||||
|
||||
char uart_getchar()
|
||||
{
|
||||
1f4: 78 01 00 00 mvhi r1,0x0
|
||||
1f8: 38 21 02 8c ori r1,r1,0x28c
|
||||
1fc: 28 22 00 00 lw r2,(r1+0)
|
||||
while (! (uart0->ucr & UART_DR)) ;
|
||||
200: 28 41 00 00 lw r1,(r2+0)
|
||||
204: 20 21 00 01 andi r1,r1,0x1
|
||||
208: 44 20 ff fe be r1,r0,200 <uart_getchar+0xc>
|
||||
return uart0->rxtx;
|
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20c: 28 41 00 04 lw r1,(r2+4)
|
||||
}
|
||||
210: 20 21 00 ff andi r1,r1,0xff
|
||||
214: c3 a0 00 00 ret
|
||||
|
||||
00000218 <uart_putchar>:
|
||||
|
||||
void uart_putchar(char c)
|
||||
{
|
||||
218: 78 02 00 00 mvhi r2,0x0
|
||||
21c: 38 42 02 8c ori r2,r2,0x28c
|
||||
220: 28 43 00 00 lw r3,(r2+0)
|
||||
224: 20 21 00 ff andi r1,r1,0xff
|
||||
while (uart0->ucr & UART_BUSY) ;
|
||||
228: 28 62 00 00 lw r2,(r3+0)
|
||||
22c: 20 42 00 10 andi r2,r2,0x10
|
||||
230: 5c 40 ff fe bne r2,r0,228 <uart_putchar+0x10>
|
||||
uart0->rxtx = c;
|
||||
234: 58 61 00 04 sw (r3+4),r1
|
||||
}
|
||||
238: c3 a0 00 00 ret
|
||||
|
||||
0000023c <uart_putstr>:
|
||||
|
||||
void uart_putstr(char *str)
|
||||
{
|
||||
char *c = str;
|
||||
while(*c) {
|
||||
23c: 40 24 00 00 lbu r4,(r1+0)
|
||||
240: 44 80 00 0b be r4,r0,26c <uart_putstr+0x30>
|
||||
244: 78 02 00 00 mvhi r2,0x0
|
||||
248: 38 42 02 8c ori r2,r2,0x28c
|
||||
24c: 28 43 00 00 lw r3,(r2+0)
|
||||
return uart0->rxtx;
|
||||
}
|
||||
|
||||
void uart_putchar(char c)
|
||||
{
|
||||
while (uart0->ucr & UART_BUSY) ;
|
||||
250: 28 62 00 00 lw r2,(r3+0)
|
||||
254: 20 42 00 10 andi r2,r2,0x10
|
||||
258: 5c 40 ff fe bne r2,r0,250 <uart_putstr+0x14>
|
||||
uart0->rxtx = c;
|
||||
25c: 58 64 00 04 sw (r3+4),r4
|
||||
void uart_putstr(char *str)
|
||||
{
|
||||
char *c = str;
|
||||
while(*c) {
|
||||
uart_putchar(*c);
|
||||
c++;
|
||||
260: 34 21 00 01 addi r1,r1,1
|
||||
}
|
||||
|
||||
void uart_putstr(char *str)
|
||||
{
|
||||
char *c = str;
|
||||
while(*c) {
|
||||
264: 40 24 00 00 lbu r4,(r1+0)
|
||||
268: 5c 82 ff fa bne r4,r2,250 <uart_putstr+0x14>
|
||||
26c: c3 a0 00 00 ret
|
||||
@@ -1,44 +0,0 @@
|
||||
S00D0000696D6167652E7372656314
|
||||
S113000098000000D00000007801000038210000B2
|
||||
S1130010D0E10000F80000033400000034000000C8
|
||||
S1130020781C00003B9C0FFC781A00003B5A02A08D
|
||||
S11300307801000038210298780300003863029C9C
|
||||
S1130040442300045820000034210004E3FFFFFD92
|
||||
S1130050340100003402000034030000F800001DE5
|
||||
S113006034010001D0010000C3A000003401000FDE
|
||||
S1130070D0210000C3A0000034010000D001000022
|
||||
S1130080C3A00000C0200000E0000000379CFFF87F
|
||||
S11300905B8B00085B9D0004F80000573C2B0008B4
|
||||
S11300A0F8000055B56108003C2B0008F800005228
|
||||
S11300B0B56108003C2B0008F800004FB56108004A
|
||||
S11300C02B9D00042B8B0008379C0008C3A0000064
|
||||
S11300D0379CFFE45B8B001C5B8C00185B8D001469
|
||||
S11300E05B8E00105B8F000C5B9000085B9D00042E
|
||||
S11300F0F8000040340D00673401002A340E007506
|
||||
S1130100340F006478100000442D0008442E0016BB
|
||||
S1130110442F000ABA00080038210270F800004891
|
||||
S1130120F80000355C2DFFFAFBFFFFD9FBFFFFD67B
|
||||
S1130130F8000031E3FFFFFCFBFFFFD5B8205800B7
|
||||
S1130140FBFFFFD3B5616000516CFFF64161000015
|
||||
S1130150356B0001F8000031558BFFFDF8000026D7
|
||||
S1130160E3FFFFF1FBFFFFCAB8205800FBFFFFC805
|
||||
S1130170B5616000516CFFEBF800001F31610000B5
|
||||
S1130180356B0001558BFFFDF800001BE3FFFFE614
|
||||
S113019078020000384202903803C350284200001D
|
||||
S11301A0882308005841001034010000584100140D
|
||||
S11301B03401000A5841000C2841000C20210001A0
|
||||
S11301C04420FFFEC3A00000780100003821029003
|
||||
S11301D0282100003802C3505822000434020000D1
|
||||
S11301E0582200083402000E58220000C3A0000068
|
||||
S11301F0C3A00000780100003821028C28220000EE
|
||||
S113020028410000202100014420FFFE2841000471
|
||||
S1130210202100FFC3A00000780200003842028CB5
|
||||
S113022028430000202100FF286200002042001023
|
||||
S11302305C40FFFE58610004C3A00000402400009D
|
||||
S11302404480000B780200003842028C28430000EE
|
||||
S113025028620000204200105C40FFFE5864000445
|
||||
S113026034210001402400005C82FFFAC3A0000096
|
||||
S11302702A2A53414B432F626F6F746C6F6164651C
|
||||
S10F0280722A2A203E200D0A0000000013
|
||||
S10F028CF0000000F0010000F00200008F
|
||||
S9030000FC
|
||||
@@ -52,8 +52,8 @@ initial begin
|
||||
|
||||
$dumpfile("system_tb.vcd");
|
||||
//$monitor("%b,%b,%b,%b",clk,rst,uart_txd,uart_rxd);
|
||||
// $dumpvars(-1, dut);
|
||||
$dumpvars(-1,clk,rst,uart_txd,uart_rxd);
|
||||
$dumpvars(-1, dut);
|
||||
//$dumpvars(-1,clk,rst,uart_txd,uart_rxd);
|
||||
// reset
|
||||
#0 rst <= 0;
|
||||
#80 rst <= 1;
|
||||
|
||||
Reference in New Issue
Block a user