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Adding plasma example

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This commit is contained in:
Carlos Camargo
2010-04-21 20:01:38 -05:00
parent f80360a678
commit 22c469585b
59 changed files with 18082 additions and 0 deletions
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29
plasma/logic/simulation/output.txt Normal file
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Greetings from the bootloader Apr 21 2010 19:05:48:
Waiting for binary image linked at 0x10000000
Other Menu Options:
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash
>
Waiting for binary image linked at 0x10000000
Other Menu Options:
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash
> 4

29
plasma/logic/simulation/plasma_3e_TB.do Normal file
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vlib work
vmap work
vcom -93 -work work ../mlite_pack.vhd
vcom -93 -work work ../plasma.vhd
vcom -93 -work work ../alu.vhd
vcom -93 -work work ../control.vhd
vcom -93 -work work ../mem_ctrl.vhd
vcom -93 -work work ../mult.vhd
vcom -93 -work work ../shifter.vhd
vcom -93 -work work ../bus_mux.vhd
vcom -93 -work work ../ddr_ctrl.vhd
vcom -93 -work work ../mlite_cpu.vhd
vcom -93 -work work ../pc_next.vhd
vcom -93 -work work ../cache.vhd
vcom -93 -work work ../eth_dma.vhd
vcom -93 -work work ../pipeline.vhd
vcom -93 -work work ../reg_bank.vhd
vcom -93 -work work ../uart.vhd
vcom -93 -work work ../plasma_3e.vhd
vcom -93 -work work ../ram_image.vhd
vcom -93 -work work ../tbench.vhd
vsim -t 1ps tbench
view wave
add wave *
view structure
view signals
run 15ms

283
plasma/logic/simulation/transcript Normal file
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# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-21-generic
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do plasma_3e_TB.do
# Reading /home/opt/cad/modeltech/linux/../modelsim.ini
# "work" maps to directory work. (Default mapping)
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package mlite_pack
# -- Compiling package body mlite_pack
# -- Loading package mlite_pack
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity plasma
# -- Compiling architecture logic of plasma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity alu
# -- Compiling architecture logic of alu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity control
# -- Compiling architecture logic of control
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity mem_ctrl
# -- Compiling architecture logic of mem_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity mult
# -- Compiling architecture logic of mult
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity shifter
# -- Compiling architecture logic of shifter
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity bus_mux
# -- Compiling architecture logic of bus_mux
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity ddr_ctrl
# -- Compiling architecture logic of ddr_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity mlite_cpu
# -- Compiling architecture logic of mlite_cpu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pc_next
# -- Compiling architecture logic of pc_next
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package mlite_pack
# -- Compiling entity cache
# -- Compiling architecture logic of cache
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity eth_dma
# -- Compiling architecture logic of eth_dma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pipeline
# -- Compiling architecture logic of pipeline
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity reg_bank
# -- Compiling architecture ram_block of reg_bank
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity uart
# -- Compiling architecture logic of uart
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity plasma_3e
# -- Compiling architecture logic of plasma_3e
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Loading package vcomponents
# -- Compiling entity ram
# -- Compiling architecture logic of ram
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity tbench
# -- Compiling architecture logic of tbench
# vsim -t 1ps tbench
# Loading /home/opt/cad/modeltech/linux/../std.standard
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_1164(body)
# Loading work.mlite_pack(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_arith(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_unsigned(body)
# Loading work.tbench(logic)
# Loading work.plasma(logic)
# Loading work.mlite_cpu(logic)
# Loading work.pc_next(logic)
# Loading work.mem_ctrl(logic)
# Loading work.control(logic)
# Loading work.reg_bank(ram_block)
# Loading work.bus_mux(logic)
# Loading work.alu(logic)
# Loading work.shifter(logic)
# Loading work.mult(logic)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vcomponents
# Loading work.cache(logic)
# Loading /home/opt/cad/modeltech/linux/../synopsys.attributes
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_misc(body)
# Loading work.ram(logic)
# Loading /home/opt/cad/modeltech/linux/../std.textio(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_timing(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_primitives(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vpkg(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.ramb16_s9(ramb16_s9_v)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_textio(body)
# Loading work.uart(logic)
# Loading work.eth_dma(logic)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u3_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 2 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# Break key hit
# Simulation stop requested.