diff --git a/Examples/blink/logic/Makefile b/Examples/blink/logic/Makefile
new file mode 100644
index 0000000..82c1822
--- /dev/null
+++ b/Examples/blink/logic/Makefile
@@ -0,0 +1,74 @@
+DESIGN          = blink
+PINS            = $(DESIGN).ucf
+DEVICE          = xc3s250e-VQ100-4
+BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
+                  -g CRC:enable -g StartUpClk:CCLK
+
+SIM_CMD         = /opt/cad/modeltech/bin/vsim 
+SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
+#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
+SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
+SAKC_IP         = 192.168.254.101
+
+SRC             = $(DESIGN).v 
+ 
+all:            bits
+
+remake:         clean-build all
+
+clean:
+	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
+	rm *.bit
+
+clean-build: clean
+	rm -rf build
+
+cleanall:   clean
+	rm -rf build $(DESIGN).bit
+
+bits:           $(DESIGN).bit
+
+#
+# Synthesis
+#
+build/project.src:
+	@[ -d build ] || mkdir build
+	@rm -f $@
+	for i in $(SRC); do echo verilog work ../$$i >> $@; done
+	for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
+
+build/project.xst: build/project.src
+	echo "run" > $@
+	echo "-top $(DESIGN) " >> $@
+	echo "-p $(DEVICE)" >> $@
+	echo "-opt_mode Area" >> $@
+	echo "-opt_level 1" >> $@
+	echo "-ifn project.src" >> $@
+	echo "-ifmt mixed" >> $@
+	echo "-ofn project.ngc" >> $@
+	echo "-ofmt NGC" >> $@
+	echo "-rtlview yes" >> $@
+
+build/project.ngc: build/project.xst $(SRC)
+	cd build && xst -ifn project.xst -ofn project.log
+
+build/project.ngd: build/project.ngc $(PINS)
+	cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
+
+build/project.ncd: build/project.ngd
+	cd build && map -pr b -p $(DEVICE) project
+
+build/project_r.ncd: build/project.ncd
+	cd build && par -w project project_r.ncd
+
+build/project_r.twr: build/project_r.ncd
+	cd build && trce -v 25 project_r.ncd project.pcf
+
+$(DESIGN).bit:  build/project_r.ncd build/project_r.twr
+	cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
+	@mv -f build/project_r.bit $@
+sim: 
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do 
+
+upload: $(DESIGN).bit
+	scp $(DESIGN).bit root@$(SAKC_IP): 
diff --git a/Examples/blink/logic/blink.ucf b/Examples/blink/logic/blink.ucf
new file mode 100644
index 0000000..9165876
--- /dev/null
+++ b/Examples/blink/logic/blink.ucf
@@ -0,0 +1,43 @@
+NET clk   LOC = "P38";
+NET reset LOC = "P71";
+NET led   LOC = "P44";
+
+#ADDRESS BUS
+#NET "addr<12>" LOC = "P90";
+#NET "addr<11>" LOC = "P91";
+#NET "addr<10>" LOC = "P85";
+#NET "addr<9>" LOC = "P92";
+#NET "addr<8>" LOC = "P94";
+#NET "addr<7>" LOC = "P95";
+#NET "addr<6>" LOC = "P98";
+#NET "addr<5>" LOC = "P3";
+#NET "addr<4>" LOC = "P2";
+#NET "addr<3>" LOC = "P78";
+#NET "addr<2>" LOC = "P79";
+#NET "addr<1>" LOC = "P83";
+#NET "addr<0>" LOC = "P84";
+
+#DATA BUS
+#NET "sram_data<7>"  LOC = "P4";
+#NET "sram_data<6>"  LOC = "P5";
+#NET "sram_data<5>"  LOC = "P9";
+#NET "sram_data<4>"  LOC = "P10";
+#NET "sram_data<3>"  LOC = "P11";
+#NET "sram_data<2>"  LOC = "P12";
+#NET "sram_data<1>"  LOC = "P15";
+#NET "sram_data<0>"  LOC = "P16";
+
+#CONTROL BUS
+#NET "nwe"   LOC = "P88";
+#NET "noe"   LOC = "P86";
+#NET "ncs"   LOC = "P69";
+
+#ADC
+#NET "ADC_EOC"    LOC = "P17";
+#NET "ADC_SCLK"   LOC = "P18";
+#NET "ADC_SDIN"   LOC = "P22";
+#NET "ADC_SDOUT"  LOC = "P23";
+#NET "ADC_CS"     LOC = "P24";
+#NET "ADC_CSTART" LOC = "P26";
+
+
diff --git a/Examples/blink/logic/blink.v b/Examples/blink/logic/blink.v
new file mode 100644
index 0000000..1a03068
--- /dev/null
+++ b/Examples/blink/logic/blink.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+module blink(clk, reset, led);
+  parameter     B = (7);
+
+  input            clk, reset;
+  output           led;
+
+  reg [24:0]  counter;
+  always @(posedge clk) begin
+    if (reset)
+      counter <= {25{1'b0}};
+    else
+      counter <= counter + 1;
+  end 
+  assign led = counter[24];
+
+endmodule
+