Fixing Makefile errors

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

@@ -1,14 +1,17 @@
 library verilog;
 use verilog.vl_types.all;
 entity sram_bus is
+    generic(
+        B               : integer := 7
+    );
     port(
         clk             : in     vl_logic;
-        reset           : in     vl_logic;
+        sram_data       : inout  vl_logic_vector;
+        addr            : in     vl_logic_vector(12 downto 0);
+        nwe             : in     vl_logic;
         ncs             : in     vl_logic;
         noe             : in     vl_logic;
-        nwe             : in     vl_logic;
-        led             : out    vl_logic;
-        sram_data       : inout  vl_logic_vector(7 downto 0);
-        addr            : in     vl_logic_vector(12 downto 0)
+        reset           : in     vl_logic;
+        led             : out    vl_logic
     );
 end sram_bus;