Fixing Makefile errors

Examples/blink/logic/Makefile

@@ -74,7 +74,7 @@ $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 	@mv -f build/project_r.bit $@
 
 build/project_r.v: build/project_r.ncd
-	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd  -w project.v
+	cd build &&  ngd2ver project.ngd  -w project.v
 
 modelsim: 
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
@@ -83,7 +83,7 @@ timesim: build/project_r.v
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
 
 iversim:
-	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
+	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
 	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
 	gtkwave simulation/$(DESIGN)_TB.vcd&
 

Examples/blink/logic/blink_TB.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module blink_TB_v;
+module blink_TB;
 
    reg  clk;
    reg  reset;

Examples/sram/logic/Makefile

@@ -29,7 +29,7 @@ remake:         clean-build all
 
 clean:
 	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
-	rm *.bit
+	rm -rf *.bit
 
 clean-build: clean
 	rm -rf build
@@ -80,7 +80,7 @@ $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 	@mv -f build/project_r.bit $@
 
 build/project_r.v: build/project_r.ncd
-	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd  -w project.v
+	cd build && ngd2ver project.ngd  -w project.v
 
 modelsim: 
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do

Examples/sram/logic/simulation/transcript

@@ -8,49 +8,26 @@
 # //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
 # //  AND IS SUBJECT TO LICENSE TERMS.
 # //
-# do sram_bus_TIMING_TB.do 
+# do sram_bus_TB.do 
 # ** Warning: (vlib-34) Library already exists at "work".
 # Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
 # -- Compiling module sram_bus
-# -- Compiling module glbl
 # -- Compiling module sram_bus_TB
-# ** Warning: glbl.v(5): 'glbl' already exists.
 # -- Compiling module glbl
 # 
 # Top level modules:
-# 	glbl
 # 	sram_bus_TB
+# 	glbl
 # vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl 
 # Loading work.sram_bus_TB
 # Loading work.sram_bus
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
+# Loading /opt/cad/modeltech/xilinx/verilog/unisims_ver.RAMB16_S2
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
 # Loading work.glbl
 # ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
 #         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
 #         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
-# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
 # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
 # .main_pane.workspace
 # .main_pane.signals.interior.cs

Examples/sram/logic/simulation/work/_info

@@ -11,24 +11,27 @@ L0 5
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 vsram_bus
-IhWan4YkPClmK5z;GkOZUS2
+I4L5C3LJ<U_bBN0U__mYo>0
-V7bnNHP1kz?3UaZfjPj4WE1
+V7R>S0^PdJz?6eY;E[l1^E2
-w1273543976
+w1273543761
-F../build/project.v
+F../sram_bus.v
-L0 37
+L0 2
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 vsram_bus_TB
 IeNSImUgW[X4l`QoUVUKI`3
 V<VFiY^801Z<UUJ?^z?JM20
-w1273543928
+w1273676679
 F../sram_bus_TB.v
 L0 3
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 nsram_bus_@t@b
 vsram_bus_TB_v
 IA=m;kT@<eh:`ekMlOPXX@0

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

@@ -1,14 +1,17 @@
 library verilog;
 use verilog.vl_types.all;
 entity sram_bus is
+    generic(
+        B               : integer := 7
+    );
     port(
         clk             : in     vl_logic;
-        reset           : in     vl_logic;
+        sram_data       : inout  vl_logic_vector;
+        addr            : in     vl_logic_vector(12 downto 0);
+        nwe             : in     vl_logic;
         ncs             : in     vl_logic;
         noe             : in     vl_logic;
-        nwe             : in     vl_logic;
+        reset           : in     vl_logic;
-        led             : out    vl_logic;
+        led             : out    vl_logic
-        sram_data       : inout  vl_logic_vector(7 downto 0);
-        addr            : in     vl_logic_vector(12 downto 0)
     );
 end sram_bus;