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Adding diagrams to DOCS and fixing someting source code.

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Juan64Bits
2010-04-14 21:45:30 -05:00
parent bde2a0a3cb
commit 47c949c5d3
12 changed files with 12 additions and 11 deletions
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16
Examples/ADC/logic/ADC_peripheral.v
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@@ -17,8 +17,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
wire [7:0] rdBus1;
reg [7:0] wrBus2;
reg [10:0] addr2;
reg we1=0;
reg we2=0;
reg we1=0, we2=0;
wire we;
//Control registers
@@ -40,12 +39,13 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
//TEMPS
reg [9:0] SIZEB1=0; // Temporal for buffer size
reg [9:0] SIZEB2=0; // Temporal for buffer size
wire[9:0] subSIZEB; // Temporal for subtraction SIZEB1-SIZEB2
reg [2:0] CMD_OFFSET=0; // Channel offset counter MOD8
wire[2:0] CMD_OFFSETt; // Channel offset to use
wire[3:0] CMD_ADCt; // Temporal for channel offset
assign ADC_CSTART = 1'b1;
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus1), // Port A 8-bit Data Output
@@ -216,7 +216,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
4: begin loadB <= 0; initB<=0; w_st0<= 0; end
endcase
end
// Reception Buffer
always @(posedge clk)
if(reset)
@@ -245,14 +245,14 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
2: begin
//Write data on BRAM (LOW)
wrBus2[7:0] <= out_buffer[7:0];
addr2 <= 4+2*(SIZEB1-SIZEB2);
addr2 <= {subSIZEB,1'b0};
we2 <= 1; w_st2 <= 3;
end
3: begin we2 <= 0; w_st2 <= 4; end
4: begin
//Write data on BRAM (HI)
wrBus2[7:0] <= {CMD_OFFSETt,2'b00,out_buffer[9:8]};
addr2 <= 5+2*(SIZEB1-SIZEB2);
wrBus2[7:0] <= out_buffer[9:8];
addr2 <= {subSIZEB,1'b1};
we2 <= 1; w_st2 <= 5;
end
5: begin
@@ -261,6 +261,8 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
endcase
end
assign subSIZEB = SIZEB1-SIZEB2;
// ADC channel offset, counter MOD8
always @(posedge clk)
if(fullB | reset)