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Updating examples to Board changes, adding irq driver demo

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This commit is contained in:
Carlos Camargo
2010-06-11 08:06:13 -05:00
parent c8b70e5307
commit 5041c0eb60
41 changed files with 2263 additions and 145 deletions
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7
Examples/sram/logic/sram_bus.ucf
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@@ -1,6 +1,7 @@
NET clk LOC = "P38";
NET reset LOC = "P71";
NET led LOC = "P44";
NET clk LOC = "P38";
NET reset LOC = "P30";
NET led LOC = "P44";
NET irq_pin LOC = "P71";
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

7
Examples/sram/logic/sram_bus.v
View File

@@ -1,11 +1,12 @@
`timescale 1ns / 1ps
module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led, irq_pin);
parameter B = (7);
input clk, nwe, ncs, noe, reset;
input [12:0] addr;
inout [B:0] sram_data;
output led;
input irq_pin;
// synchronize signals
reg sncs, snwe;
@@ -39,7 +40,7 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
// write access cpu to bram
always @(posedge clk)
if(reset) {w_st, we, wdBus} <= 0;
if(~reset) {w_st, we, wdBus} <= 0;
else begin
wdBus <= buffer_data;
case (w_st)
@@ -71,7 +72,7 @@ RAMB16_S2 ba3( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
reg [24:0] counter;
always @(posedge clk) begin
if (reset)
if (~reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;