Updating examples to Board changes, adding irq driver demo

lm32/logic/sakc/cores/uart/doc/Makefile

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+TEX=uart.tex
+
+DVI=$(TEX:.tex=.dvi)
+PS=$(TEX:.tex=.ps)
+PDF=$(TEX:.tex=.pdf)
+AUX=$(TEX:.tex=.aux)
+LOG=$(TEX:.tex=.log)
+
+all: $(PDF)
+
+%.dvi: %.tex
+	latex $<
+
+%.ps: %.dvi
+	dvips $<
+
+%.pdf: %.ps
+	ps2pdf $<
+
+clean:
+	rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
+
+.PHONY: clean

lm32/logic/sakc/cores/uart/doc/uart.tex

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+\documentclass[a4paper,11pt]{article}
+\usepackage{fullpage}
+\usepackage[latin1]{inputenc}
+\usepackage[T1]{fontenc}
+\usepackage[normalem]{ulem}
+\usepackage[english]{babel}
+\usepackage{listings,babel}
+\lstset{breaklines=true,basicstyle=\ttfamily}
+\usepackage{graphicx}
+\usepackage{moreverb}
+\usepackage{amsmath}
+\usepackage{url}
+\usepackage{tabularx}
+
+\title{Simple UART}
+\author{S\'ebastien Bourdeauducq}
+\date{December 2009}
+\begin{document}
+\setlength{\parindent}{0pt}
+\setlength{\parskip}{5pt}
+\maketitle{}
+\section{Specifications}
+The UART is based on a very simple design from Das Labor. Its purpose is basically to provide a debug console.
+
+The UART operates with 8 bits per character, no parity, and 1 stop bit. The default baudrate is configured during synthesis and can be modified at runtime using the divisor register.
+
+The divisor is computed as follows :
+\begin{equation*}
+\text{divisor} = \frac{\text{Clock frequency (Hz)}}{16 \cdot \text{Bitrate (bps)}}
+\end{equation*}
+
+\section{Registers}
+\begin{tabularx}{\textwidth}{|l|l|l|X|}
+\hline
+\bf{Offset} & \bf{Read/Write} & \bf{Default} & \bf{Description} \\
+\hline
+0x0 & RW & 0x00 & Data register. Received bytes and bytes to transmit are read/written from/to this register. \\
+\hline
+0x4 & RW & for default bitrate & Divisor register (for bitrate selection). \\
+\hline
+\end{tabularx}\\
+
+\section{Interrupts}
+The core has two active-high edge-sensitive interrupts outputs.
+
+The ``RX'' interrupt is sent whenever a new character is received. The CPU should then read the data register immediately. If a new character is sent before the CPU has had time to read it, the first character will be lost.
+
+The ``TX'' interrupt is sent as soon as the UART finished transmitting a character. When the CPU has written to the data register, it must wait for the interrupt before writing again.
+
+\section{Using the core}
+Connect the CSR signals and the interrupts to the system bus and the interrupt controller. The \verb!uart_txd! and \verb!uart_rxd! signals should go to the FPGA pads. You must also provide the desired default baudrate and the system clock frequency in Hz using the parameters.
+
+\section*{Copyright notice}
+Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
+Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
+
+\end{document}