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Code Activity

Updating examples to Board changes, adding irq driver demo

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This commit is contained in:
Carlos Camargo
2010-06-11 08:06:13 -05:00
parent c8b70e5307
commit 5041c0eb60
41 changed files with 2263 additions and 145 deletions
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1
plasma/logic/mlite_pack.vhd
View File

@@ -425,6 +425,7 @@ package mlite_pack is
nwe : in std_logic;
noe : in std_logic;
ncs : in std_logic;
irq_pin : in std_logic;
led : out std_logic);
end component; --plasma

5
plasma/logic/plasma.ucf
View File

@@ -1,8 +1,9 @@
NET clk LOC = "P38";
NET clk_in LOC = "P38";
NET rst_in LOC = "P30";
NET uart_write LOC = "P67";
NET uart_read LOC = "P68";
NET led LOC = "P44";
NET led LOC = "P44";
NET irq_pin LOC = "P71";
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

5
plasma/logic/plasma.vhd
View File

@@ -41,6 +41,7 @@ entity plasma is
nwe : in std_logic;
noe : in std_logic;
ncs : in std_logic;
irq_pin : in std_logic;
led : out std_logic
);
end; --entity plasma
@@ -147,6 +148,9 @@ begin
variable bus_dec : std_logic_vector(6 downto 0);
begin
bus_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
-- if cpu_address(30 downto 28) = "000" then
-- cpu_data_r <= ram_data_r;
-- else
case bus_dec is
when "000----" => cpu_data_r <= ram_data_r;
when "0100000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
@@ -158,6 +162,7 @@ begin
when "0100110" => cpu_data_r <= ZERO;
when others => cpu_data_r <= ZERO;
end case;
-- end if;
end process;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

3
plasma/logic/plasma_TB.vhd
View File

@@ -28,8 +28,8 @@ architecture logic of tbench is
signal nwe : std_logic;
signal noe : std_logic;
signal ncs : std_logic;
signal irq_pin : std_logic;
signal led : std_logic;
signal TxD : std_logic;
signal RxD : std_logic;
@@ -51,6 +51,7 @@ begin --architecture
nwe => nwe,
noe => noe,
ncs => ncs,
irq_pin => irq_pin,
led => led
);

176
plasma/logic/ram.vhd Normal file
View File

@@ -0,0 +1,176 @@
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 13;
begin
generic_ram:
if memory_type /= "ALTERA_LPM" generate
begin
--Simulate a synchronous RAM
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable mem_size : natural := 2 ** ADDRESS_WIDTH;
variable data : std_logic_vector(31 downto 0);
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to mem_size/4 - 1) of word;
variable storage : storage_array;
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) := data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) := data;
end if;
end if;
data_read <= data;
end process;
end generate; --generic_ram
altera_ram:
if memory_type = "ALTERA_LPM" generate
signal byte_we : std_logic_vector(3 downto 0);
begin
byte_we <= write_byte_enable when enable = '1' else "0000";
lpm_ram_io_component0 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code0.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(31 downto 24),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(3),
q => data_read(31 downto 24));
lpm_ram_io_component1 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code1.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(23 downto 16),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(2),
q => data_read(23 downto 16));
lpm_ram_io_component2 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code2.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(15 downto 8),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(1),
q => data_read(15 downto 8));
lpm_ram_io_component3 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code3.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(7 downto 0),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(0),
q => data_read(7 downto 0));
end generate; --altera_ram
--For XILINX see ram_xilinx.vhd
end; --architecture logic

182
plasma/logic/ram_image.vhd
View File

@@ -45,27 +45,27 @@ INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"3c34ac343c34a42434a42434a42434a02434a02434a02434a02434a024343c27",
INIT_05 => X"8cac343caf008c34a730009434a330009034af008ca730009434a3300090ac34",
INIT_06 => X"82240c00142400100080afafaf270003ac3c1030008c343c0008af008c34af00",
INIT_07 => X"26240c2608240c00102c3002242400afafafaf2727038f8f8f0000140082260c",
INIT_08 => X"2703008f8c3c10000caf2730038c343c2703008f240caf2727038f8f8f8f0216",
INIT_09 => X"000000000000000000000000000000000024038c001424ac00008c243c3c243c",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"1c24001030008c24ac24ac9424003c00180003241c24a4248c0018ac2400003c",
INIT_05 => X"a00024241028302400a03c24243c3c0003001030008cacac242400003c000300",
INIT_06 => X"100010000c00102a0200260c24af08af2424240000afafafafaf270103001424",
INIT_07 => X"240c001a001427038f8f8f8f8f8f8f02240c240c000824102c24142c24142e24",
INIT_08 => X"008c34ac3c3c24240c3c240c3caf0cafafafafafafafafaf270008260c24240c",
INIT_09 => X"3c240c3c240c3c240c3c3c3c3c3c3c003c3c0c003c240c3c3c1430248c3c1030",
INIT_0A => X"0000142c2400000c240c3c270c260c260c260c260c240c3c240c3c240c3c240c",
INIT_0B => X"000c000c00000c240c3c3c08240c3c000c000c8e0000008c0024003c3c102c26",
INIT_0C => X"0200000010000c240c3c3c080002a208000c000c00000c240c3c0008923c08ae",
INIT_0D => X"000010000c240c3c3c080216a002260c00000010000c240c3c3c080216260c90",
INIT_0E => X"260c8c02240c3c00000010000c240c3c3c08240c000c000c0014002490020000",
INIT_0F => X"120008a23c243c3c08240c3c021402240c000c260c8c021032021002240c000c",
INIT_10 => X"3c083c0c003c000c0014343c000c240c3c3c0800003c0016260c262610000c3c",
INIT_11 => X"008c343c3c08240c000c000c2608240c3c000c020c240c3c00000c240c3c020c",
INIT_12 => X"82000c2682000c241400100082260c00240800100080afafaf270003ac001030",
INIT_13 => X"038f8f8f8f0216260c2424142c3002242400afafafaf272703008f8f8f001400",
INIT_14 => X"038c0014ac00248c3c24243c3c2703008f8c3c10000caf2730038c343c240827",
INIT_15 => X"6531006e706e724f303030206e6569612020740a00616d20423a20616f430a24",
INIT_16 => X"617965613673647475350a62697965340079617965330a7769796532006f6179",
INIT_17 => X"0a3d6541206820720a3e00616f446f42316f4600753900736838006979656137",
INIT_18 => X"00000000000000000000000000000000000037336820660a0d786e6e0a786e75",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
@@ -122,28 +122,28 @@ INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"026482420264820264820264820264a2026582026482026482026482026403bd",
INIT_05 => X"62624202a2004262a242004262a242004262a20082a242004262a24200a28242",
INIT_06 => X"04040000511180400082b0b1bfbd00e044024042006243020000a2006263a200",
INIT_07 => X"108400100084000040824412111080b0b1b2bfbdbde0b0b1bf00004000021000",
INIT_08 => X"bde000bf4202400000bfbd42e0424202bde000bf0400bfbdbde0b0b1b2bf1211",
INIT_09 => X"000000000000000000040000802400800042e0a2006463404500624402054302",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"c0c60040420062636284658205620205c000e084c0a582c6a200c0a202a20502",
INIT_05 => X"c2e5070740a285634040036642020300e000404200828283020382040200e000",
INIT_06 => X"54405300000040220312310090b000bf1514130000b1b2b3b4b5bd00e004c3c6",
INIT_07 => X"040000208095bde0b0b1b2b3b4b5bf4004000400000090404282404282400250",
INIT_08 => X"00434283020403840004840004b000b1b2b3b4b5b6b7bebfbd12003100040400",
INIT_09 => X"024400024400024400021e171615144002060000048400041543420382146063",
INIT_0A => X"0000404242400000440002c400e400c400a40084004400024400024400024400",
INIT_0B => X"4000400040000044000202004400024000000044008000444383030402406203",
INIT_0C => X"4200004040000044000202000040500040004000400000440002000044020050",
INIT_0D => X"0040400000440002020000136251100000004040000044000202000011100044",
INIT_0E => X"300044504400020000404000004400020200040040000000a0a683a543420000",
INIT_0F => X"1100005013111202004400020060130400400030004450400200601304004000",
INIT_10 => X"0200060000040000004363030000440002020000400240535200101040000002",
INIT_11 => X"0062a30502000400400000000300440002400040004400024000004400020000",
INIT_12 => X"02400010020000045100400002100040110080400082b1bfb0bd00e0a4004042",
INIT_13 => X"e0b0b1b2bf12111000646440624312111080bfb0b1b2bdbde000b0b1bf004000",
INIT_14 => X"e0a20083404584820563440302bde000bf6203400000bfbd42e06263030400bd",
INIT_15 => X"6d2e007374752074303078616b206d7262666957007320666f0a006474205342",
INIT_16 => X"64206d772e73646f6d2e007974206d2e007464206d2e006f74206d2e00726420",
INIT_17 => X"56207364006569654120007320526d2032702e006d2e0075652e0074206d772e",
INIT_18 => X"0000000000000000000000000000000000003834207769430a3e2074433e2065",
INIT_19 => X"0000000000000000000000000000000000000004000080240080000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
@@ -195,32 +195,32 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
INIT_01 => X"000000000000000000000000000000000000012000002000d800d800ff700000",
INIT_00 => X"00000000000000000000000000000000ff00000100ff18000e000e000c008c00",
INIT_01 => X"000000000000000000000000000000000000022000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"31030030300300220200210200200200000400000400000400000400000420ff",
INIT_05 => X"000055550000000300ff000002000000000400000000ff000002000000000031",
INIT_06 => X"00000000000080000000000000ff10000020ff00000000200000000000000000",
INIT_07 => X"ff0000ff0100000000000010ff009000000000ff00000000001000ff00000000",
INIT_08 => X"000000000020ff000100ff000000002000000000000000ff00000000000010ff",
INIT_09 => X"000000000000000000200000002028000000000000ff00001000000400100400",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"ffff00ff00000000000000000018301800000000ff0000ff0000000000282830",
INIT_05 => X"001000000000000c4000000c0c0000000000ff00000000000000202030000000",
INIT_06 => X"002000000200000090190002ff00000000000088900000000000ff100021ffff",
INIT_07 => X"0002000080ff00000000000000000010000200020000ff0000ffff00ffff00ff",
INIT_08 => X"000000002030000a02000a02000002000000000000000000ff9100ff02000002",
INIT_09 => X"000a02000a02000a02000000000000f810000028100a02000000ff3c00000000",
INIT_0A => X"90000000ff8000020b02000b020b020b020b020b020b02000b02000b02000b02",
INIT_0B => X"200280002000000b020000010b0200200200000000000000100c100000ff00ff",
INIT_0C => X"10108088ff00000c0200000100f80001200280002000000b0200000100000100",
INIT_0D => X"28300000000c0200000188ff00180002888098ff00000c0200000110ff000200",
INIT_0E => X"000000100c02008880980000000c0200000100022002000010ff200000101020",
INIT_0F => X"0080020010271000010c020088ff180002200200000010ff0088001800022002",
INIT_10 => X"000100002810200000ff561200000c0200000100f81080ff0002ff00ff000210",
INIT_11 => X"000000200001000220022000ff010b0200200220000b02009000000b02002002",
INIT_12 => X"0020020000000200ff00000000000220000280000000000000ff00000010ff00",
INIT_13 => X"000000000010ffff02000000000010ff009000000000ff00001000000000ff00",
INIT_14 => X"000000ff00100000100c0c0000000000000020ff000200ff0000000020000200",
INIT_15 => X"6f20003a69204d680a303174656c6179696f6e61006866726f0000656c624100",
INIT_16 => X"0a726f20200a72207020007465776f20006520726f20007265776f2000642072",
INIT_17 => X"6100736400786e736400006866202066387920007020006d63200065776f2020",
INIT_18 => X"0404040404070404070606060606060505003e353169726f002068206f206820",
INIT_19 => X"0000000000000000000000000000000000000020000000202800000804040404",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
@@ -272,32 +272,32 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a00c800e000dc00d001",
INIT_01 => X"504c4844403c3834302c2824201c18141000082410200060125c1058fc005450",
INIT_00 => X"4c4844403c3834302c2824201c181410980e000704fd2a00b800d000b400b001",
INIT_01 => X"504c4844403c3834302c2824201c18141000812410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"31340030303000221400211200201000141400131300121200111100101000f8",
INIT_05 => X"000055550400003802ff00001800ff00001804000002ff00001600ff00000031",
INIT_06 => X"000dc800030a210d0000101418e021080000fc020000200000c6040000200400",
INIT_07 => X"fc57c8fc0030c800050a0f06fc1c211014181ce020081014182100f6000001c8",
INIT_08 => X"180800100000fd001010e801080020001808001049c810e820081014181c06f4",
INIT_09 => X"000000000000000000001010200000207084080000fa0400210000dc0000bc00",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"f4fe00fc80000004000200004021004011000802fb0400fe00000700ff214000",
INIT_05 => X"00213037020a0fbf210800c7c00000000800fc8000000000d020214000000800",
INIT_06 => X"0c210e00880012102100013cc910db28080d0a212114181c2024d0210802f7ff",
INIT_07 => X"083c000821d930081014181c202428210a3c0d3c00d4a9111a9fed1abff10ad0",
INIT_08 => X"000050000000ff984600844600109314181c2024282c3034c802d8ff3c08203c",
INIT_09 => X"00f84600e04600b0460000000000000900028021009c4600000cff1c00001001",
INIT_0A => X"2100c20ad0210088d84600b446a846984680466c465846004046002846001046",
INIT_0B => X"214621b12100c5fc46000037244600214600b10000080000213c800000d416cf",
INIT_0C => X"212121219a00c50c4600003700090036214621b12100c5fc4600006d00003700",
INIT_0D => X"21217600c50c4600003721fb002101882121218900c50c4600003721fb013c00",
INIT_0E => X"04b100211c46002121211e00c50c460000370a3c214600b121fb210100212121",
INIT_0F => X"0b21010010100000371c460021f42b203c214604b10021f00f210e2b203c2146",
INIT_10 => X"0037028f210021a3001f783400c5204600003700090021f30188ff01fb008300",
INIT_11 => X"0000200000370a3c214621b1cf61244600214621b1f046002100c5dc4600213c",
INIT_12 => X"00213c0100003c0df8000d0000013c210a5721160000141810e000080021fc02",
INIT_13 => X"081014181c06f8fc3c5730020a0f06fc1c211c101418e020082110141800f500",
INIT_14 => X"080000fb0021040000b4940000180800100000fd008310e80108002000493c20",
INIT_15 => X"724d000a6f4f656500303020646967206e726769000a6c6f740000726f6f4b84",
INIT_16 => X"0065726d52006561204a00652072724d000a6265724d00642072724d000a7765",
INIT_17 => X"6c002072003e20736400000a6c7444724b2043000a44000a6b43000a72726d52",
INIT_18 => X"d8d8d8d8d8e4d8d840e09c5848180cd8b000203632746d6e0000656975006569",
INIT_19 => X"0000000000000000000000000000000000000000101020000020703cd8d8d8d8",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",

119
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---------------------------------------------------------------------
-- TITLE: Test Bench
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a test bench for testing the Plasma CPU core.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity tbench is
end; --entity tbench
architecture logic of tbench is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
constant log_file : string :=
-- "UNUSED";
"output.txt";
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
begin --architecture
--Uncomment the line below to test interrupts
interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
clk <= not clk after 50 ns;
reset <= '0' after 500 ns;
pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause <= pause1 or pause2;
gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '1',
use_cache => '1',
log_file => log_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic