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Code

Fixing some errors on SAKC Examples

This commit is contained in:
carlos 2010-10-07 11:53:01 -05:00
parent 46e28e9714
commit 568f2182ef
24 changed files with 41739 additions and 55199 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Examples/sram_gpio/src/Makefile
View File

@ -20,17 +20,17 @@ COMMON_OBJECTS = $(COMMON_SOURCES:.c=.o)
NANO_IP = 192.168.254.101
jz_init_sram: $(COMMON_OBJECTS)
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_init_sram.c -o jz_init_sram
jz_init_sram: $(COMMON_OBJECTS) jz_init_sram.o
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_init_sram.o -o jz_init_sram
jz_test_gpio: $(COMMON_OBJECTS)
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_test_gpio.c -o jz_test_gpio
jz_test_gpio: $(COMMON_OBJECTS) jz_test_gpio.o
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_test_gpio.o -o jz_test_gpio
enable_rx: $(COMMON_OBJECTS)
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_rx.c -o enable_rx
enable_rx: $(COMMON_OBJECTS) enable_rx.o
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_rx.o -o enable_rx
enable_irq: $(COMMON_OBJECTS)
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_irq.c -o enable_irq
enable_irq: $(COMMON_OBJECTS) enable_irq.o
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) enable_irq.o -o enable_irq
.c.o:
$(CC) -c $(CCFLAGS) $< -o $@

21
Examples/sram_gpio/src/jz_init_sram.c
View File

@ -52,26 +52,13 @@ main ()
printf ("Writing Memory..\n");
// srand48(0x3c);
for (i = 0; i < FPGA_SIZE/4; i++)
// virt_addr[i] = (lrand48() & 0x00ff);
virt_addr[i] = (lrand48() & 0x00ff);
for (i = 0; i < 0xff; i++)
virt_addr[i] = i;
printf ("Reading Memory..\n");
srand48(0x3c);
for (i = 0; i < FPGA_SIZE/4; i++){
printf("%X\n", virt_addr[i]);
if (virt_addr[i] != (lrand48() & 0x00ff)){
printf ("FPGA - Xburst connection test failed on Address:0x%x\n", i);
return 1; /* Error */
}
for (i = 0; i < 0xff; i++){
printf("W:%X, R:%X\n", i, virt_addr[i]);
}
printf ("%d\n", i);
printf ("FPGA - Xburst connection test passed\n");
return 0;
}

7
Examples/sram_gpio/src/jz_test_gpio.c
View File

@ -23,21 +23,18 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include "jz47xx_gpio.h"
//#define TEST_PORT JZ_GPIO_PORT_C
//#define TEST_PIN 17
#define TEST_PORT JZ_GPIO_PORT_C
#define TEST_PIN 17
int
main (int argc,char *argv[])
{
int TEST_PORT, TEST_PIN;
if(argc != 3){
fprintf(stderr,"\nUsage: %s TEST_PIN_PORT(A=0, B=1, C=2, D=3) TEST_PIN \n",argv[0]);
}
TEST_PORT = ;
TEST_PIN = ;
JZ_PIO *pio = jz_gpio_map (TEST_PORT);
if (!pio)

50511
KICAD_design_files/SAKC_PCB_v2/$savepcb.000
View File

File diff suppressed because it is too large Load Diff

45986
KICAD_design_files/SAKC_PCB_v2/$savepcb.brd
View File

File diff suppressed because it is too large Load Diff

4
KICAD_design_files/SAKC_PCB_v2/CONNECTORS.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/CONNECTORS.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/CPU.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 3 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/CPU.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 3 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/D_CONVERTER.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 5 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/D_CONVERTER.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 5 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/FPGA.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 8 9
Title "noname.sch"
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/FPGA.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 8 9
Title "noname.sch"
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/LCD.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 9 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/LCD.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 9 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/MEMORY.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 6 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/MEMORY.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 6 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

90
KICAD_design_files/SAKC_PCB_v2/POWER_SUPPLY.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 2 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -47,14 +47,20 @@ Wire Wire Line
1250 1750 1250 1950
Connection ~ 5550 5950
Wire Wire Line
5150 5950 5950 5950
5150 5950 5550 5950
Wire Wire Line
5550 5950 5950 5950
Wire Wire Line
4050 5150 4050 5300
Wire Wire Line
5550 6650 5550 7050
Connection ~ 5150 5300
Wire Wire Line
4800 5300 6400 5300
4800 5300 5150 5300
Wire Wire Line
5150 5300 5950 5300
Wire Wire Line
5950 5300 6400 5300
Wire Wire Line
5950 5300 5950 5450
Wire Wire Line
@ -76,20 +82,26 @@ Wire Wire Line
8225 2200 8000 2200
Connection ~ 9350 5450
Wire Wire Line
9350 5350 9350 5500
9350 5350 9350 5450
Wire Wire Line
9350 5450 9350 5500
Wire Wire Line
5900 2150 5900 2250
Wire Wire Line
7900 2400 7900 2300
7900 2300 7900 2300
Connection ~ 4100 2300
Wire Wire Line
4250 2300 3800 2300
4250 2300 4100 2300
Wire Wire Line
7800 5700 7800 5450
4100 2300 3800 2300
Wire Wire Line
7800 5450 7800 5450
Wire Wire Line
7800 5450 8350 5450
Wire Wire Line
9000 5450 9350 5450
9000 5450 9100 5450
Wire Wire Line
9100 5450 9350 5450
Wire Wire Line
2100 3600 2200 3600
Wire Wire Line
@ -105,7 +117,7 @@ Wire Wire Line
Wire Wire Line
9025 2200 8875 2200
Wire Wire Line
5000 2400 5000 2350
4990 2350 5000 2350
Wire Wire Line
5000 2350 5100 2350
Wire Wire Line
@ -125,11 +137,13 @@ Wire Wire Line
Wire Wire Line
5250 2250 5000 2250
Wire Wire Line
2900 2300 2900 2350
2900 2300 2900 2300
Wire Wire Line
7900 2300 8075 2300
Wire Wire Line
4250 3650 3150 3650
4250 3650 3600 3650
Wire Wire Line
3600 3650 3150 3650
Connection ~ 3600 3650
Wire Wire Line
4250 4050 4250 4200
@ -142,15 +156,21 @@ Wire Wire Line
Wire Wire Line
8050 5500 8050 5400
Wire Wire Line
8350 5400 7850 5400
8350 5400 8050 5400
Wire Wire Line
8050 5400 7850 5400
Wire Wire Line
7850 5400 7850 5350
Connection ~ 8050 5400
Wire Wire Line
5900 2300 6750 2300
5900 2300 6500 2300
Wire Wire Line
6500 2300 6750 2300
Connection ~ 6500 2300
Wire Wire Line
9425 2300 8875 2300
9425 2300 9280 2300
Wire Wire Line
9280 2300 8875 2300
Wire Wire Line
8875 2200 8875 2100
Wire Wire Line
@ -192,9 +212,9 @@ Text HLabel 1250 1750 3 20 BiDi ~ 0
VRTC
Text GLabel 1250 1950 1 20 BiDi ~ 0
VRTC
Text GLabel 6400 5200 3 20 BiDi ~ 0
Text GLabel 6400 5200 0 20 BiDi ~ 0
VRTC
Text GLabel 4050 5150 3 20 BiDi ~ 0
Text GLabel 4050 5150 0 20 BiDi ~ 0
3.3V
Text GLabel 5550 7050 1 20 BiDi ~ 0
GND
@ -234,9 +254,9 @@ F 1 "BATTERY" V 5550 5950 50 0000 C CNN
1 5550 6350
0 1 1 0
$EndComp
Text GLabel 10200 2140 3 20 BiDi ~ 0
Text GLabel 10200 2140 0 20 BiDi ~ 0
3.3V
Text GLabel 10200 3400 1 20 BiDi ~ 0
Text GLabel 10200 3400 2 20 BiDi ~ 0
GND
$Comp
L R R31
@ -256,7 +276,7 @@ F 1 "LED" H 10200 2400 50 0000 C CNN
1 10200 2500
0 1 1 0
$EndComp
Text GLabel 7900 2400 1 20 BiDi ~ 0
Text GLabel 7900 2300 0 20 BiDi ~ 0
GND
Text GLabel 1200 1950 1 20 BiDi ~ 0
GND
@ -266,9 +286,9 @@ Text GLabel 1150 1950 1 20 BiDi ~ 0
BAT_V
Text HLabel 1150 1750 3 20 BiDi ~ 0
BAT_V
Text GLabel 9350 6050 1 20 BiDi ~ 0
Text GLabel 9350 6050 2 20 BiDi ~ 0
GND
Text GLabel 7800 5700 1 20 BiDi ~ 0
Text GLabel 7800 5450 0 20 BiDi ~ 0
GND
$Comp
L C C57
@ -279,39 +299,39 @@ F 1 "100n" H 9330 2460 50 0000 L CNN
1 9280 2560
1 0 0 -1
$EndComp
Text GLabel 9280 2810 1 20 BiDi ~ 0
Text GLabel 9280 2810 2 20 BiDi ~ 0
GND
Text GLabel 2100 3600 0 20 BiDi ~ 0
GND
Text GLabel 5050 4250 1 20 BiDi ~ 0
Text GLabel 5050 4250 2 20 BiDi ~ 0
GND
Text GLabel 4250 4200 1 20 BiDi ~ 0
Text GLabel 4250 4200 2 20 BiDi ~ 0
GND
Text GLabel 3600 4200 1 20 BiDi ~ 0
Text GLabel 3600 4200 2 20 BiDi ~ 0
GND
Text GLabel 6500 2800 1 20 BiDi ~ 0
Text GLabel 6500 2800 2 20 BiDi ~ 0
GND
Text GLabel 5000 2400 1 20 BiDi ~ 0
Text GLabel 4990 2350 0 20 BiDi ~ 0
GND
Text GLabel 4100 2800 1 20 BiDi ~ 0
Text GLabel 4100 2800 2 20 BiDi ~ 0
GND
Text GLabel 2900 2350 1 20 BiDi ~ 0
Text GLabel 2900 2300 0 20 BiDi ~ 0
GND
Text GLabel 2350 3600 2 20 BiDi ~ 0
BAT_V
Text GLabel 3150 3650 0 20 BiDi ~ 0
BAT_V
Text GLabel 7850 5350 3 20 BiDi ~ 0
Text GLabel 7850 5350 0 20 BiDi ~ 0
3.3V
Text GLabel 9100 5350 3 20 BiDi ~ 0
Text GLabel 9100 5350 0 20 BiDi ~ 0
2V5
Text GLabel 9350 5350 3 20 BiDi ~ 0
Text GLabel 9350 5350 0 20 BiDi ~ 0
2.5V
Text GLabel 9425 2300 2 20 BiDi ~ 0
1.2V
Text GLabel 9025 2200 2 20 BiDi ~ 0
1.2V
Text GLabel 8875 2100 3 20 BiDi ~ 0
Text GLabel 8875 2100 2 20 BiDi ~ 0
1V2
Text GLabel 8000 2200 0 20 BiDi ~ 0
BAT_V
@ -319,7 +339,7 @@ Text GLabel 6750 2300 2 20 BiDi ~ 0
3.3V
Text GLabel 6000 2250 2 20 BiDi ~ 0
3.3V
Text GLabel 5900 2150 3 20 BiDi ~ 0
Text GLabel 5900 2150 0 20 BiDi ~ 0
3V3
Text GLabel 5000 2250 0 20 BiDi ~ 0
BAT_V

90
KICAD_design_files/SAKC_PCB_v2/POWER_SUPPLY.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 2 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -47,14 +47,20 @@ Wire Wire Line
1250 1750 1250 1950
Connection ~ 5550 5950
Wire Wire Line
5150 5950 5950 5950
5150 5950 5550 5950
Wire Wire Line
5550 5950 5950 5950
Wire Wire Line
4050 5150 4050 5300
Wire Wire Line
5550 6650 5550 7050
Connection ~ 5150 5300
Wire Wire Line
4800 5300 6400 5300
4800 5300 5150 5300
Wire Wire Line
5150 5300 5950 5300
Wire Wire Line
5950 5300 6400 5300
Wire Wire Line
5950 5300 5950 5450
Wire Wire Line
@ -76,20 +82,26 @@ Wire Wire Line
8225 2200 8000 2200
Connection ~ 9350 5450
Wire Wire Line
9350 5350 9350 5500
9350 5350 9350 5450
Wire Wire Line
9350 5450 9350 5500
Wire Wire Line
5900 2150 5900 2250
Wire Wire Line
7900 2400 7900 2300
7900 2300 7900 2300
Connection ~ 4100 2300
Wire Wire Line
4250 2300 3800 2300
4250 2300 4100 2300
Wire Wire Line
7800 5700 7800 5450
4100 2300 3800 2300
Wire Wire Line
7800 5450 7800 5450
Wire Wire Line
7800 5450 8350 5450
Wire Wire Line
9000 5450 9350 5450
9000 5450 9100 5450
Wire Wire Line
9100 5450 9350 5450
Wire Wire Line
2100 3600 2200 3600
Wire Wire Line
@ -105,7 +117,7 @@ Wire Wire Line
Wire Wire Line
9025 2200 8875 2200
Wire Wire Line
5000 2400 5000 2350
4990 2350 5000 2350
Wire Wire Line
5000 2350 5100 2350
Wire Wire Line
@ -125,11 +137,13 @@ Wire Wire Line
Wire Wire Line
5250 2250 5000 2250
Wire Wire Line
2900 2300 2900 2350
2900 2300 2900 2300
Wire Wire Line
7900 2300 8075 2300
Wire Wire Line
4250 3650 3150 3650
4250 3650 3600 3650
Wire Wire Line
3600 3650 3150 3650
Connection ~ 3600 3650
Wire Wire Line
4250 4050 4250 4200
@ -142,15 +156,21 @@ Wire Wire Line
Wire Wire Line
8050 5500 8050 5400
Wire Wire Line
8350 5400 7850 5400
8350 5400 8050 5400
Wire Wire Line
8050 5400 7850 5400
Wire Wire Line
7850 5400 7850 5350
Connection ~ 8050 5400
Wire Wire Line
5900 2300 6750 2300
5900 2300 6500 2300
Wire Wire Line
6500 2300 6750 2300
Connection ~ 6500 2300
Wire Wire Line
9425 2300 8875 2300
9425 2300 9280 2300
Wire Wire Line
9280 2300 8875 2300
Wire Wire Line
8875 2200 8875 2100
Wire Wire Line
@ -192,9 +212,9 @@ Text HLabel 1250 1750 3 20 BiDi ~ 0
VRTC
Text GLabel 1250 1950 1 20 BiDi ~ 0
VRTC
Text GLabel 6400 5200 3 20 BiDi ~ 0
Text GLabel 6400 5200 0 20 BiDi ~ 0
VRTC
Text GLabel 4050 5150 3 20 BiDi ~ 0
Text GLabel 4050 5150 0 20 BiDi ~ 0
3.3V
Text GLabel 5550 7050 1 20 BiDi ~ 0
GND
@ -234,9 +254,9 @@ F 1 "BATTERY" V 5550 5950 50 0000 C CNN
1 5550 6350
0 1 1 0
$EndComp
Text GLabel 10200 2140 3 20 BiDi ~ 0
Text GLabel 10200 2140 0 20 BiDi ~ 0
3.3V
Text GLabel 10200 3400 1 20 BiDi ~ 0
Text GLabel 10200 3400 2 20 BiDi ~ 0
GND
$Comp
L R R31
@ -256,7 +276,7 @@ F 1 "LED" H 10200 2400 50 0000 C CNN
1 10200 2500
0 1 1 0
$EndComp
Text GLabel 7900 2400 1 20 BiDi ~ 0
Text GLabel 7900 2300 0 20 BiDi ~ 0
GND
Text GLabel 1200 1950 1 20 BiDi ~ 0
GND
@ -266,9 +286,9 @@ Text GLabel 1150 1950 1 20 BiDi ~ 0
BAT_V
Text HLabel 1150 1750 3 20 BiDi ~ 0
BAT_V
Text GLabel 9350 6050 1 20 BiDi ~ 0
Text GLabel 9350 6050 2 20 BiDi ~ 0
GND
Text GLabel 7800 5700 1 20 BiDi ~ 0
Text GLabel 7800 5450 0 20 BiDi ~ 0
GND
$Comp
L C C57
@ -279,39 +299,39 @@ F 1 "100n" H 9330 2460 50 0000 L CNN
1 9280 2560
1 0 0 -1
$EndComp
Text GLabel 9280 2810 1 20 BiDi ~ 0
Text GLabel 9280 2810 2 20 BiDi ~ 0
GND
Text GLabel 2100 3600 0 20 BiDi ~ 0
GND
Text GLabel 5050 4250 1 20 BiDi ~ 0
Text GLabel 5050 4250 2 20 BiDi ~ 0
GND
Text GLabel 4250 4200 1 20 BiDi ~ 0
Text GLabel 4250 4200 2 20 BiDi ~ 0
GND
Text GLabel 3600 4200 1 20 BiDi ~ 0
Text GLabel 3600 4200 2 20 BiDi ~ 0
GND
Text GLabel 6500 2800 1 20 BiDi ~ 0
Text GLabel 6500 2800 2 20 BiDi ~ 0
GND
Text GLabel 5000 2400 1 20 BiDi ~ 0
Text GLabel 4990 2350 0 20 BiDi ~ 0
GND
Text GLabel 4100 2800 1 20 BiDi ~ 0
Text GLabel 4100 2800 2 20 BiDi ~ 0
GND
Text GLabel 2900 2350 1 20 BiDi ~ 0
Text GLabel 2900 2300 0 20 BiDi ~ 0
GND
Text GLabel 2350 3600 2 20 BiDi ~ 0
BAT_V
Text GLabel 3150 3650 0 20 BiDi ~ 0
BAT_V
Text GLabel 7850 5350 3 20 BiDi ~ 0
Text GLabel 7850 5350 0 20 BiDi ~ 0
3.3V
Text GLabel 9100 5350 3 20 BiDi ~ 0
Text GLabel 9100 5350 0 20 BiDi ~ 0
2V5
Text GLabel 9350 5350 3 20 BiDi ~ 0
Text GLabel 9350 5350 0 20 BiDi ~ 0
2.5V
Text GLabel 9425 2300 2 20 BiDi ~ 0
1.2V
Text GLabel 9025 2200 2 20 BiDi ~ 0
1.2V
Text GLabel 8875 2100 3 20 BiDi ~ 0
Text GLabel 8875 2100 2 20 BiDi ~ 0
1V2
Text GLabel 8000 2200 0 20 BiDi ~ 0
BAT_V
@ -319,7 +339,7 @@ Text GLabel 6750 2300 2 20 BiDi ~ 0
3.3V
Text GLabel 6000 2250 2 20 BiDi ~ 0
3.3V
Text GLabel 5900 2150 3 20 BiDi ~ 0
Text GLabel 5900 2150 0 20 BiDi ~ 0
3V3
Text GLabel 5000 2250 0 20 BiDi ~ 0
BAT_V

4
KICAD_design_files/SAKC_PCB_v2/SAKC.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 1 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

153
KICAD_design_files/SAKC_PCB_v2/SAKC.pro
View File

@ -1,5 +1,5 @@
update=Mon 04 Oct 2010 04:37:43 PM COT
last_client=eeschema
update=Wed 06 Oct 2010 10:06:17 AM COT
last_client=pcbnew
[general]
version=1
RootSch=SAKC.sch
@ -11,41 +11,88 @@ version=1
NetIExt=.net
[cvpcb/libraries]
EquName1=devcms
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=../kicad_components/header_40
LibName3=device
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=contrib
LibName28=valves
LibName29=Design files/x25x64mb
LibName30=Design files/mcp3008
[pcbnew]
version=1
PadDrlX=200
PadDimH=600
PadDimV=600
ViaDiam=236
ViaDril=118
ViaAltD=250
MViaDia=200
MViaDrl=80
Isol=75
Countlayer=2
Lpiste=75
RouteTo=15
RouteBo=0
TypeVia=3
Segm45=1
Racc45=1
BoardThickness=630
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=79
HPGLnum=1
HPGdiam=15
HPGLSpd=20
HPGLrec=2
HPGLorg=0
VEgarde=100
DrawLar=79
EdgeLar=79
TxtLar=120
MSegLar=79
WpenSer=10
LastNetListRead=
[pcbnew/libraries]
LibDir=./N_MODELS/
LibName1=./N_MODELS/D8
@ -222,68 +269,4 @@ LibName171=./N_MODELS/UF2
LibName172=./N_MODELS/Y1
LibName173=./N_MODELS/Y2
LibName174=./N_MODELS/Y3
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=../kicad_components/header_40
LibName3=device
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=contrib
LibName28=valves
LibName29=Design files/x25x64mb
LibName30=Design files/mcp3008

4
KICAD_design_files/SAKC_PCB_v2/SAKC.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 1 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/UART_USB_I2C.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:47 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:47:58 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""

4
KICAD_design_files/SAKC_PCB_v2/UART_USB_I2C.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 05 Oct 2010 09:52:54 AM COT
EESchema Schematic File Version 2 date Wed 06 Oct 2010 09:50:01 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -35,7 +35,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "5 oct 2010"
Date "6 oct 2010"
Rev ""
Comp ""
Comment1 ""