From 5fbd9db02f9bc966892cf290383d940e7e990da4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9sar=20Pedraza?= Date: Tue, 12 Oct 2010 10:21:30 -0500 Subject: [PATCH] fixed logic for Evalfit peripheral --- Examples/ehw4/logic/evalfit_peripheral.vhd | 52 +++++++++++----------- Examples/ehw4/logic/reg_bank.v | 8 ++-- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/Examples/ehw4/logic/evalfit_peripheral.vhd b/Examples/ehw4/logic/evalfit_peripheral.vhd index f6cca81..485a606 100644 --- a/Examples/ehw4/logic/evalfit_peripheral.vhd +++ b/Examples/ehw4/logic/evalfit_peripheral.vhd @@ -3,15 +3,15 @@ -- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables *** -- Funciona hasta con 14 vars. -- mapa: - -- 0 - 0x3F Cromosoma + -- 0 - 0x3F Cromosoma (cada uno con 64-bit) -- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB. --- Cromosoma en memoria - -- bit bit Contenido +-- Mapa de cromosoma: + -- bit bit Contenido -- 28 a 31 Nivel del arbol - -- 32 a 47 LUT o tabla del arbol - -- 48 a 63 Variables de entrada del arbol (4 bits por variable) + -- 32 a 47 LUT o tabla del arbol LUT(32)MSB, LUT(47)LSB, + -- 48 a 63 Variables de entrada del arbol (4 bits por variable) 48-51 MSB, 60-63 LSB library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -25,12 +25,12 @@ entity evalfit_peripheral is Port ( clk, reset, habilita: in STD_LOGIC; maxcombs : in STD_LOGIC_VECTOR (0 to 15); nivel_max : in STD_LOGIC_VECTOR (0 to 3); - peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63); - peripheral_mem_en : out std_logic; - peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63); - peripheral_mem_we : out STD_LOGIC; - peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8); - evalfit3_estado : out std_logic_vector(0 to 7); + peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63); + peripheral_mem_en : out std_logic; + peripheral_mem_out: out STD_LOGIC_VECTOR (0 to 63); + peripheral_mem_we : out STD_LOGIC; + peripheral_mem_addr: out STD_LOGIC_VECTOR (0 to 8); + evalfit3_estado : out std_logic_vector(0 to 15); errores : out STD_LOGIC_VECTOR (0 to 15); fin_ack : out std_logic; reg0_s : out STD_LOGIC_VECTOR (0 to 31); @@ -54,7 +54,7 @@ begin when "0101" => return ent(10); when "0110" => return ent(9); when "0111" => return ent(8); - when "1000" => return ent(7); + when "1000" => return ent(7); when "1001" => return ent(6); when "1010" => return ent(5); when "1011" => return ent(4); @@ -95,7 +95,7 @@ signal ep, es: estado; signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3); signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1); signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15); -signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 7); +signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 15); signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8); begin @@ -132,18 +132,20 @@ peripheral_mem_we <= '0'; peripheral_mem_en <= '0'; errores_sig <= errores_aux; nivel_sig <= nivel_reg; -estado_evalf3_sig <= x"FF"; +estado_evalf3_sig <= x"FFFF"; case ep is when reset1 => --poner la memoria a 0000 WE_n2_sig <= "1111"; WE_n3_sig <= "1111"; WE_n4_sig <= "1111"; conta2_sig <= (others => '0'); + estado_evalf3_sig <= x"0001"; es <= reset2; when reset2 => DI_n2 <= "0000"; DI_n3 <= "0000"; DI_n4 <= "0000"; + estado_evalf3_sig <= x"0002"; if(conta2 = maxcombs)then WE_n2_sig <= "0000"; WE_n3_sig <= "0000"; @@ -173,7 +175,7 @@ case ep is es <= proceso; peripheral_mem_en <= '1'; end if; - estado_evalf3_sig <= x"01"; + estado_evalf3_sig <= x"0003"; when proceso => peripheral_mem_en <= '1'; @@ -206,14 +208,14 @@ case ep is peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1; peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1; nivel_sig <= nivel; - estado_evalf3_sig <= x"02"; + estado_evalf3_sig <= peripheral_mem_in(48 to 63);--x"FFE" & nivel;----x"02"; when n1 => peripheral_mem_en <= '1'; c1_sig <= c1 + 1; peripheral_mem_addr_sig <= peripheral_mem_addr_aux; es <= proceso; - estado_evalf3_sig <= x"03"; + estado_evalf3_sig <= x"0004"; when n2 => WE_n2_sig(conv_integer(c2)) <= '1'; @@ -222,7 +224,7 @@ case ep is peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida es <= precuenta; conta2_sig <= (others => '0'); - estado_evalf3_sig <= x"04"; + estado_evalf3_sig <= x"0005"; when n3 => WE_n3_sig(conv_integer(c3)) <= '1'; @@ -231,7 +233,7 @@ case ep is peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- es <= precuenta; conta2_sig <= (others => '0'); - estado_evalf3_sig <= x"05"; + estado_evalf3_sig <= x"0006"; when n4 => WE_n4_sig(conv_integer(c4)) <= '1'; @@ -240,7 +242,7 @@ case ep is peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- es <= precuenta; conta2_sig <= (others => '0'); - estado_evalf3_sig <= x"06"; + estado_evalf3_sig <= x"0007"; when precuenta => WE_n2_sig <= WE_n2; @@ -254,7 +256,7 @@ case ep is conta_sig <= conta; conta2_sig <= conta + 1; es <= cuenta; - estado_evalf3_sig <= x"07"; + estado_evalf3_sig <= x"0008"; when cuenta => DI_n2(conv_integer(c2)) <= salida_nivel(2); @@ -292,7 +294,7 @@ case ep is errores_sig <= errores_aux; end if; - estado_evalf3_sig <= x"08"; + estado_evalf3_sig <= x"0009"; when final => if(nivel_reg = "0010")then @@ -305,7 +307,7 @@ case ep is peripheral_mem_en <= '1'; peripheral_mem_addr_sig <= peripheral_mem_addr_crom; es <= proceso; - estado_evalf3_sig <= x"09"; + estado_evalf3_sig <= x"000A"; when final2 => if(habilita = '1') then @@ -314,7 +316,7 @@ case ep is es <= inicio; end if; fin_ack_sig <= '1'; - estado_evalf3_sig <= x"0A"; + estado_evalf3_sig <= x"000B"; when others => es <= inicio; end case; @@ -346,7 +348,7 @@ begin peripheral_mem_addr_crom <= "000000000"; errores_aux <= (others => '0'); nivel_reg <= "0000"; - estado_evalf3 <= x"00"; + estado_evalf3 <= x"0000"; elsif(rising_edge(clk))then ep <= es; c1 <= c1_sig; diff --git a/Examples/ehw4/logic/reg_bank.v b/Examples/ehw4/logic/reg_bank.v index b51c7fc..26ed4ab 100644 --- a/Examples/ehw4/logic/reg_bank.v +++ b/Examples/ehw4/logic/reg_bank.v @@ -29,12 +29,11 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg // Read control always @(posedge clk) if(reset) - rdBus = 8'h00; + rdBus = 8'h00; else begin - rdBus = reg_bank[address]; + rdBus = reg_bank[address]; end - // Store Inputs always @(posedge clk) begin @@ -67,7 +66,7 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg reg_bank[20] = error[7:0]; reg_bank[21] = error[15:8]; - reg_bank[22] = { 4'b0, status}; + reg_bank[22] = {4'b0, status}; // reg_bank[23] = regMT[7:0]; // reg_bank[24] = regMT[15:8]; @@ -76,7 +75,6 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg end end - assign max_com[7:0] = reg_bank[26]; assign max_com[15:8] = reg_bank[27]; assign max_lev = reg_bank[28];