mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Adding lm32 demo to SAKC project
This commit is contained in:
Carlos Camargo
50
lm32/logic/sakc/firmware/ddr-phaser/Makefile
Normal file
50
lm32/logic/sakc/firmware/ddr-phaser/Makefile
Normal file
@@ -0,0 +1,50 @@
|
||||
LM32_CC=lm32-elf-gcc
|
||||
LM32_LD=lm32-elf-ld
|
||||
LM32_OBJCOPY=lm32-elf-objcopy
|
||||
LM32_OBJDUMP=lm32-elf-objdump
|
||||
|
||||
SREC2VRAM ?= ../../tools/srec2vram/srec2vram
|
||||
|
||||
VRAMFILE=image.ram
|
||||
|
||||
CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
|
||||
LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
|
||||
SEGMENTS = -j .text -j .rodata -j .data
|
||||
|
||||
all: $(VRAMFILE)
|
||||
|
||||
crt0ram.o: crt0ram.S
|
||||
$(LM32_CC) $(CFLAGS) -c crt0ram.S
|
||||
|
||||
main.o: main.c
|
||||
$(LM32_CC) $(CFLAGS) -c main.c
|
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|
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spike_hw.o: spike_hw.c
|
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$(LM32_CC) $(CFLAGS) -c spike_hw.c
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|
||||
image: crt0ram.o main.o spike_hw.o
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||||
$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o spike_hw.o
|
||||
|
||||
image.lst: image
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||||
$(LM32_OBJDUMP) -h -S $< > $@
|
||||
|
||||
image.bin: image
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||||
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.bin
|
||||
|
||||
image.srec: image image.lst
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||||
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
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||||
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||||
$(VHDLFILE): image.srec
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||||
$(SREC2VHDL) image.srec > $(VHDLFILE)
|
||||
|
||||
$(VRAMFILE): image.srec
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||||
$(SREC2VRAM) image.srec 0x00000000 0x1000 > $(VRAMFILE)
|
||||
|
||||
clean:
|
||||
rm -f image image.lst image.bin image.srec image.map *.o *.d
|
||||
|
||||
DEPS := $(wildcard *.d)
|
||||
ifneq ($(DEPS),)
|
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include $(DEPS)
|
||||
endif
|
||||
|
||||
166
lm32/logic/sakc/firmware/ddr-phaser/crt0ram.S
Normal file
166
lm32/logic/sakc/firmware/ddr-phaser/crt0ram.S
Normal file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* LatticeMico32 C startup code.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* Exception handlers - Must be 32 bytes long. */
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||||
.section .text, "ax", @progbits
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.global _start
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.global irq_enable, irq_disable, irq_mask, jump, halt
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||||
_start:
|
||||
_reset_handler:
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||||
xor r0, r0, r0
|
||||
wcsr IE, r0
|
||||
mvhi r1, hi(_reset_handler)
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||||
ori r1, r1, lo(_reset_handler)
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||||
wcsr EBA, r1
|
||||
calli _crt0
|
||||
nop
|
||||
nop
|
||||
|
||||
_crt0:
|
||||
/* Setup stack and global pointer */
|
||||
mvhi sp, hi(_fstack)
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||||
ori sp, sp, lo(_fstack)
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||||
mvhi gp, hi(_gp)
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ori gp, gp, lo(_gp)
|
||||
|
||||
/* Clear BSS */
|
||||
mvhi r1, hi(_fbss)
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||||
ori r1, r1, lo(_fbss)
|
||||
mvhi r3, hi(_ebss)
|
||||
ori r3, r3, lo(_ebss)
|
||||
.clearBSS:
|
||||
be r1, r3, .callMain
|
||||
sw (r1+0), r0
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||||
addi r1, r1, 4
|
||||
bi .clearBSS
|
||||
|
||||
.callMain:
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mvi r1, 0
|
||||
mvi r2, 0
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||||
mvi r3, 0
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||||
calli main
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||||
|
||||
irq_enable:
|
||||
mvi r1, 1
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||||
wcsr IE, r1
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||||
ret
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||||
|
||||
irq_mask:
|
||||
mvi r1, 0x0000000f
|
||||
wcsr IM, r1
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||||
ret
|
||||
|
||||
irq_disable:
|
||||
mvi r1, 0
|
||||
wcsr IE, r1
|
||||
ret
|
||||
|
||||
jump:
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b r1
|
||||
|
||||
halt:
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bi halt
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||||
|
||||
/* Save all registers onto the stack */
|
||||
_save_all:
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addi sp, sp, -128
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||||
sw (sp+4), r1
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||||
sw (sp+8), r2
|
||||
sw (sp+12), r3
|
||||
sw (sp+16), r4
|
||||
sw (sp+20), r5
|
||||
sw (sp+24), r6
|
||||
sw (sp+28), r7
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||||
sw (sp+32), r8
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||||
sw (sp+36), r9
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sw (sp+40), r10
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#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
|
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sw (sp+44), r11
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sw (sp+48), r12
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||||
sw (sp+52), r13
|
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sw (sp+56), r14
|
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sw (sp+60), r15
|
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sw (sp+64), r16
|
||||
sw (sp+68), r17
|
||||
sw (sp+72), r18
|
||||
sw (sp+76), r19
|
||||
sw (sp+80), r20
|
||||
sw (sp+84), r21
|
||||
sw (sp+88), r22
|
||||
sw (sp+92), r23
|
||||
sw (sp+96), r24
|
||||
sw (sp+100), r25
|
||||
sw (sp+104), r26
|
||||
sw (sp+108), r27
|
||||
#endif
|
||||
sw (sp+120), ea
|
||||
sw (sp+124), ba
|
||||
/* ra and sp need special handling, as they have been modified */
|
||||
lw r1, (sp+128)
|
||||
sw (sp+116), r1
|
||||
mv r1, sp
|
||||
addi r1, r1, 128
|
||||
sw (sp+112), r1
|
||||
ret
|
||||
|
||||
/* Restore all registers and return from exception */
|
||||
_restore_all_and_return:
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lw r1, (sp+4)
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lw r2, (sp+8)
|
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lw r3, (sp+12)
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||||
lw r4, (sp+16)
|
||||
lw r5, (sp+20)
|
||||
lw r6, (sp+24)
|
||||
lw r7, (sp+28)
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||||
lw r8, (sp+32)
|
||||
lw r9, (sp+36)
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||||
lw r10, (sp+40)
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||||
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
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||||
lw r11, (sp+44)
|
||||
lw r12, (sp+48)
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||||
lw r13, (sp+52)
|
||||
lw r14, (sp+56)
|
||||
lw r15, (sp+60)
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||||
lw r16, (sp+64)
|
||||
lw r17, (sp+68)
|
||||
lw r18, (sp+72)
|
||||
lw r19, (sp+76)
|
||||
lw r20, (sp+80)
|
||||
lw r21, (sp+84)
|
||||
lw r22, (sp+88)
|
||||
lw r23, (sp+92)
|
||||
lw r24, (sp+96)
|
||||
lw r25, (sp+100)
|
||||
lw r26, (sp+104)
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||||
lw r27, (sp+108)
|
||||
#endif
|
||||
lw ra, (sp+116)
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||||
lw ea, (sp+120)
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||||
lw ba, (sp+124)
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||||
/* Stack pointer must be restored last, in case it has been updated */
|
||||
lw sp, (sp+112)
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eret
|
||||
|
||||
|
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1024
lm32/logic/sakc/firmware/ddr-phaser/image.ram
Normal file
1024
lm32/logic/sakc/firmware/ddr-phaser/image.ram
Normal file
File diff suppressed because it is too large
Load Diff
59
lm32/logic/sakc/firmware/ddr-phaser/linker.ld
Normal file
59
lm32/logic/sakc/firmware/ddr-phaser/linker.ld
Normal file
@@ -0,0 +1,59 @@
|
||||
OUTPUT_FORMAT("elf32-lm32")
|
||||
ENTRY(_start)
|
||||
|
||||
__DYNAMIC = 0;
|
||||
|
||||
|
||||
_BRAM_START = 0x00000000;
|
||||
_BRAM_SIZE = 0x1000;
|
||||
_BRAM_END = _BRAM_START + _BRAM_SIZE;
|
||||
|
||||
MEMORY {
|
||||
bram : ORIGIN = 0x00000000, LENGTH = 0x1000 /* 4k */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_ftext = .;
|
||||
*(.text .stub .text.* .gnu.linkonce.t.*)
|
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_etext = .;
|
||||
} > bram
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
_erodata = .;
|
||||
} > bram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
_gp = ALIGN(16);
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
_edata = .;
|
||||
} > bram
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > bram
|
||||
}
|
||||
|
||||
PROVIDE(_fstack = ORIGIN(bram) + LENGTH(bram) - 4);
|
||||
105
lm32/logic/sakc/firmware/ddr-phaser/main.c
Normal file
105
lm32/logic/sakc/firmware/ddr-phaser/main.c
Normal file
@@ -0,0 +1,105 @@
|
||||
/**
|
||||
* DDR Phase Shifter
|
||||
*/
|
||||
|
||||
#include "spike_hw.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Control DDR phase shift
|
||||
*/
|
||||
inline int ps_ready()
|
||||
{
|
||||
return (gpio0->in & (1 << 16)); // return 1 when ready, 0 otherwise
|
||||
}
|
||||
|
||||
inline void ps_inc()
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
while ( ! ps_ready() );
|
||||
|
||||
tmp = gpio0->out;
|
||||
gpio0->out = tmp | (1 << 16);
|
||||
gpio0->out = tmp;
|
||||
|
||||
while ( ! ps_ready() );
|
||||
}
|
||||
|
||||
inline void ps_dec()
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
while ( ! ps_ready() );
|
||||
|
||||
tmp = gpio0->out;
|
||||
gpio0->out = tmp | (1 << 17);
|
||||
gpio0->out = tmp;
|
||||
|
||||
while ( ! ps_ready() );
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Simple memory tester
|
||||
*
|
||||
* Returns -1 on error, 0 when OK.
|
||||
*/
|
||||
inline int memtest(uint32_t size)
|
||||
{
|
||||
volatile uint32_t *p;
|
||||
int res = 0;
|
||||
|
||||
for (p=(uint32_t *)RAM_START; p<(uint32_t *)(RAM_START+size); p++) {
|
||||
*p = (uint32_t) p;
|
||||
}
|
||||
|
||||
for (p=(uint32_t *)RAM_START; p<(uint32_t *)(RAM_START+size); p++) {
|
||||
if (*p != (uint32_t)p) {
|
||||
res = -1;
|
||||
}
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
void scan_phase(int dir, uint32_t size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<=255; i++) {
|
||||
if (memtest(size) == 0)
|
||||
uart_putchar('O');
|
||||
else
|
||||
uart_putchar('-');
|
||||
|
||||
if (dir == 1) ps_inc(); else ps_dec();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
uint32_t scan_size = 16*1024; // scan 16 kByte
|
||||
|
||||
// Initialize stuff
|
||||
uart_init();
|
||||
|
||||
uart_putstr("\r\n\r\n** SOC-LM32 DDR PAHSER **\n\n");
|
||||
uart_putstr("'O' => Memtest OK ; '-' => Memtest failed\n\n");
|
||||
uart_putstr("Press [u] for upward scan, [d] for downward\n");
|
||||
|
||||
for(;;) {
|
||||
uint8_t c = uart_getchar();
|
||||
|
||||
switch (c) {
|
||||
case 'u': // scan upward
|
||||
scan_phase(1, scan_size);
|
||||
break;
|
||||
case 'd': // scan downward
|
||||
scan_phase(-1, scan_size);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
68
lm32/logic/sakc/firmware/ddr-phaser/spike_hw.c
Normal file
68
lm32/logic/sakc/firmware/ddr-phaser/spike_hw.c
Normal file
@@ -0,0 +1,68 @@
|
||||
#include "spike_hw.h"
|
||||
|
||||
uart_t *uart0 = (uart_t *) 0xF0000000;
|
||||
timer_t *timer0 = (timer_t *) 0xF0010000;
|
||||
gpio_t *gpio0 = (gpio_t *) 0xF0020000;
|
||||
|
||||
uint32_t msec = 0;
|
||||
|
||||
/***************************************************************************
|
||||
* General utility functions
|
||||
*/
|
||||
void sleep(int msec)
|
||||
{
|
||||
uint32_t tcr;
|
||||
|
||||
// Use timer0.1
|
||||
timer0->compare1 = (FCPU/1000)*msec;
|
||||
timer0->counter1 = 0;
|
||||
timer0->tcr1 = TIMER_EN | TIMER_IRQEN;
|
||||
|
||||
do {
|
||||
//halt();
|
||||
tcr = timer0->tcr1;
|
||||
} while ( ! (tcr & TIMER_TRIG) );
|
||||
}
|
||||
|
||||
void tic_init()
|
||||
{
|
||||
// Setup timer0.0
|
||||
timer0->compare0 = (FCPU/1000);
|
||||
timer0->counter0 = 0;
|
||||
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* UART Functions
|
||||
*/
|
||||
void uart_init()
|
||||
{
|
||||
//uart0->ier = 0x00; // Interrupt Enable Register
|
||||
//uart0->lcr = 0x03; // Line Control Register: 8N1
|
||||
//uart0->mcr = 0x00; // Modem Control Register
|
||||
|
||||
// Setup Divisor register (Fclk / Baud)
|
||||
//uart0->div = (FCPU/(57600*16));
|
||||
}
|
||||
|
||||
char uart_getchar()
|
||||
{
|
||||
while (! (uart0->ucr & UART_DR)) ;
|
||||
return uart0->rxtx;
|
||||
}
|
||||
|
||||
void uart_putchar(char c)
|
||||
{
|
||||
while (uart0->ucr & UART_BUSY) ;
|
||||
uart0->rxtx = c;
|
||||
}
|
||||
|
||||
void uart_putstr(char *str)
|
||||
{
|
||||
char *c = str;
|
||||
while(*c) {
|
||||
uart_putchar(*c);
|
||||
c++;
|
||||
}
|
||||
}
|
||||
|
||||
108
lm32/logic/sakc/firmware/ddr-phaser/spike_hw.h
Normal file
108
lm32/logic/sakc/firmware/ddr-phaser/spike_hw.h
Normal file
@@ -0,0 +1,108 @@
|
||||
#ifndef SPIKEHW_H
|
||||
#define SPIKEHW_H
|
||||
|
||||
#define PROMSTART 0x00000000
|
||||
#define RAMSTART 0x00000800
|
||||
#define RAMSIZE 0x400
|
||||
#define RAMEND (RAMSTART + RAMSIZE)
|
||||
|
||||
#define RAM_START 0x40000000
|
||||
#define RAM_SIZE 0x04000000
|
||||
|
||||
#define FCPU 50000000
|
||||
|
||||
#define UART_RXBUFSIZE 32
|
||||
|
||||
/****************************************************************************
|
||||
* Types
|
||||
*/
|
||||
typedef unsigned int uint32_t; // 32 Bit
|
||||
typedef signed int int32_t; // 32 Bit
|
||||
|
||||
typedef unsigned char uint8_t; // 8 Bit
|
||||
typedef signed char int8_t; // 8 Bit
|
||||
|
||||
/****************************************************************************
|
||||
* Interrupt handling
|
||||
*/
|
||||
typedef void(*isr_ptr_t)(void);
|
||||
|
||||
void irq_enable();
|
||||
void irq_disable();
|
||||
void irq_set_mask(uint32_t mask);
|
||||
uint32_t irq_get_mak();
|
||||
|
||||
void isr_init();
|
||||
void isr_register(int irq, isr_ptr_t isr);
|
||||
void isr_unregister(int irq);
|
||||
|
||||
/****************************************************************************
|
||||
* General Stuff
|
||||
*/
|
||||
void halt();
|
||||
void jump(uint32_t addr);
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Timer
|
||||
*/
|
||||
#define TIMER_EN 0x08 // Enable Timer
|
||||
#define TIMER_AR 0x04 // Auto-Reload
|
||||
#define TIMER_IRQEN 0x02 // IRQ Enable
|
||||
#define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR)
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t tcr0;
|
||||
volatile uint32_t compare0;
|
||||
volatile uint32_t counter0;
|
||||
volatile uint32_t tcr1;
|
||||
volatile uint32_t compare1;
|
||||
volatile uint32_t counter1;
|
||||
} timer_t;
|
||||
|
||||
void msleep(uint32_t msec);
|
||||
void nsleep(uint32_t nsec);
|
||||
|
||||
void tic_init();
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* GPIO0
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t ctrl;
|
||||
volatile uint32_t dummy1;
|
||||
volatile uint32_t dummy2;
|
||||
volatile uint32_t dummy3;
|
||||
volatile uint32_t in;
|
||||
volatile uint32_t out;
|
||||
volatile uint32_t oe;
|
||||
} gpio_t;
|
||||
|
||||
/***************************************************************************
|
||||
* UART0
|
||||
*/
|
||||
#define UART_DR 0x01 // RX Data Ready
|
||||
#define UART_ERR 0x02 // RX Error
|
||||
#define UART_BUSY 0x10 // TX Busy
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t ucr;
|
||||
volatile uint32_t rxtx;
|
||||
} uart_t;
|
||||
|
||||
void uart_init();
|
||||
void uart_putchar(char c);
|
||||
void uart_putstr(char *str);
|
||||
char uart_getchar();
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Pointer to actual components
|
||||
*/
|
||||
extern timer_t *timer0;
|
||||
extern uart_t *uart0;
|
||||
extern gpio_t *gpio0;
|
||||
extern uint32_t *sram0;
|
||||
|
||||
#endif // SPIKEHW_H
|
||||
Reference in New Issue
Block a user