mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Adding lm32 demo to SAKC project
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105
lm32/logic/sakc/firmware/ddr-phaser/main.c
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105
lm32/logic/sakc/firmware/ddr-phaser/main.c
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/**
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* DDR Phase Shifter
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*/
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#include "spike_hw.h"
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/******************************************************************************
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* Control DDR phase shift
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*/
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inline int ps_ready()
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{
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return (gpio0->in & (1 << 16)); // return 1 when ready, 0 otherwise
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}
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inline void ps_inc()
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{
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uint32_t tmp;
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while ( ! ps_ready() );
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tmp = gpio0->out;
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gpio0->out = tmp | (1 << 16);
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gpio0->out = tmp;
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while ( ! ps_ready() );
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}
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inline void ps_dec()
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{
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uint32_t tmp;
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while ( ! ps_ready() );
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tmp = gpio0->out;
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gpio0->out = tmp | (1 << 17);
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gpio0->out = tmp;
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while ( ! ps_ready() );
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}
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/******************************************************************************
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* Simple memory tester
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*
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* Returns -1 on error, 0 when OK.
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*/
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inline int memtest(uint32_t size)
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{
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volatile uint32_t *p;
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int res = 0;
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for (p=(uint32_t *)RAM_START; p<(uint32_t *)(RAM_START+size); p++) {
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*p = (uint32_t) p;
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}
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for (p=(uint32_t *)RAM_START; p<(uint32_t *)(RAM_START+size); p++) {
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if (*p != (uint32_t)p) {
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res = -1;
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}
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}
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return res;
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}
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void scan_phase(int dir, uint32_t size)
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{
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int i;
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for (i=0; i<=255; i++) {
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if (memtest(size) == 0)
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uart_putchar('O');
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else
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uart_putchar('-');
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if (dir == 1) ps_inc(); else ps_dec();
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}
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}
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int main(int argc, char **argv)
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{
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uint32_t scan_size = 16*1024; // scan 16 kByte
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// Initialize stuff
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uart_init();
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uart_putstr("\r\n\r\n** SOC-LM32 DDR PAHSER **\n\n");
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uart_putstr("'O' => Memtest OK ; '-' => Memtest failed\n\n");
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uart_putstr("Press [u] for upward scan, [d] for downward\n");
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for(;;) {
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uint8_t c = uart_getchar();
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switch (c) {
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case 'u': // scan upward
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scan_phase(1, scan_size);
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break;
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case 'd': // scan downward
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scan_phase(-1, scan_size);
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break;
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}
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}
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}
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