qi-hardware/nn-usb-fpga
1
0
Fork 0
mirror of git://projects.qi-hardware.com/nn-usb-fpga.git synced 2025-04-21 12:27:27 +03:00
Code Activity

Adding lm32 demo to SAKC project

Browse Source
This commit is contained in:
Carlos Camargo
2010-05-25 21:49:58 -05:00
parent 26b0c73a84
commit 61d4408f2a
145 changed files with 27924 additions and 1501 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
lm32/logic/sakc/firmware/gdb-test/Makefile Normal file
View File

@@ -0,0 +1,43 @@
LM32_CC=lm32-elf-gcc
LM32_LD=lm32-elf-ld
LM32_OBJCOPY=lm32-elf-objcopy
LM32_OBJDUMP=lm32-elf-objdump
SREC2VRAM ?= ../../tools/srec2vram/srec2vram
VRAMFILE=image.ram
CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
SEGMENTS = -j .boot -j .text -j .rodata -j .data
all: image.srec $(VRAMFILE)
%.o: %.S
$(LM32_CC) $(CFLAGS) -c $<
%.o: %.c
$(LM32_CC) $(CFLAGS) -c $<
image: crt0gdb.o main.o soc-hw.o gdb.o gdb_uart.o
$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image $^
image.lst: image
$(LM32_OBJDUMP) -h -S $< > $@
image.bin: image
$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
image.srec: image image.lst
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
$(VRAMFILE): image.srec
$(SREC2VRAM) image.srec 0x40000000 0x100000 > $(VRAMFILE)
clean:
rm -f image image.lst image.bin image.srec image.map *.o *.d
DEPS := $(wildcard *.d)
ifneq ($(DEPS),)
include $(DEPS)
endif

290
lm32/logic/sakc/firmware/gdb-test/crt0gdb.S Normal file
View File

@@ -0,0 +1,290 @@
/*
* LatticeMico32 GDB C startup code.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* Exception handlers - Must be 32 bytes long. */
.section .boot, "ax", @progbits
.global _start
_start:
_reset_handler:
bi _crt0
nop
nop
nop
nop
nop
nop
nop
_breakpoint_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ba
mvi r1, 1
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _b_restore_all_and_return
_instruction_bus_error_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ea
mvi r1, 2
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _e_restore_all_and_return
_watchpoint_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ba
mvi r1, 3
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _b_restore_all_and_return
_data_bus_error_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ea
mvi r1, 4
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _e_restore_all_and_return
_divide_by_zero_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ea
mvi r1, 5
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _e_restore_all_and_return
_interrupt_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ea
mvi r1, 6
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _e_restore_all_and_return
_system_call_handler:
sw (sp+0), ra
calli _save_all
sw (sp+128), ea
mvi r1, 7
sw (sp+132), r1
mv r1, sp
calli _handle_exception
bi _e_restore_all_and_return
/* Program starts here */
_crt0:
/* Clear r0 */
xor r0, r0, r0
/* Clear all other regs (needed so that simulations match) */
mvi r1, 0
mvi r2, 0
mvi r3, 0
mvi r4, 0
mvi r5, 0
mvi r6, 0
mvi r7, 0
mvi r8, 0
mvi r9, 0
mvi r10, 0
mvi r11, 0
mvi r12, 0
mvi r13, 0
mvi r14, 0
mvi r15, 0
mvi r16, 0
mvi r17, 0
mvi r18, 0
mvi r19, 0
mvi r20, 0
mvi r21, 0
mvi r22, 0
mvi r23, 0
mvi r24, 0
mvi r25, 0
mvi r26, 0
mvi r27, 0
mvi r28, 0
mvi r29, 0
mvi r30, 0
mvi r31, 0
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
/* Clear BSS */
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
.clearBSS:
be r1, r3, .callMain
sw (r1+0), r0
addi r1, r1, 4
bi .clearBSS
.callMain:
mvi r1, 0
mvi r2, 0
mvi r3, 0
/* Enter debug exception handler */
mvhi ba, hi(main)
ori ba, ba, lo(main)
bi _breakpoint_handler
/* Save all registers onto the stack */
_save_all:
addi sp, sp, -136
sw (sp+0), r0
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
sw (sp+16), r4
sw (sp+20), r5
sw (sp+24), r6
sw (sp+28), r7
sw (sp+32), r8
sw (sp+36), r9
sw (sp+40), r10
sw (sp+44), r11
sw (sp+48), r12
sw (sp+52), r13
sw (sp+56), r14
sw (sp+60), r15
sw (sp+64), r16
sw (sp+68), r17
sw (sp+72), r18
sw (sp+76), r19
sw (sp+80), r20
sw (sp+84), r21
sw (sp+88), r22
sw (sp+92), r23
sw (sp+96), r24
sw (sp+100), r25
sw (sp+104), r26
sw (sp+108), r27
sw (sp+120), ea
sw (sp+124), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+136)
sw (sp+116), r1
mv r1, sp
addi r1, r1, 136
sw (sp+112), r1
ret
/* Restore all registers and return from exception */
_e_restore_all_and_return:
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
lw ra, (sp+116)
lw ba, (sp+124)
/* Restore EA from PC */
lw ea, (sp+128)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
eret
/* Restore all registers and return from breakpoint */
_b_restore_all_and_return:
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
lw ra, (sp+116)
lw ea, (sp+120)
/* Restore BA from PC */
lw ba, (sp+128)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
bret

1214
lm32/logic/sakc/firmware/gdb-test/gdb.c Normal file
View File

File diff suppressed because it is too large Load Diff

37
lm32/logic/sakc/firmware/gdb-test/gdb.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* LatticeMico32 GDB I/O.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _LM32_GDB_H
#define _LM32_GDB_H
/* Write a single character to debug host */
void _gdb_write_char (char);
/* Read and return a single character from debug host */
char _gdb_read_char (void);
/* Acknowledge interrupt that caused CPU to enter debug mode */
void _gdb_ack_interrupt (void);
#endif /* _LM32_GDB_H */

23
lm32/logic/sakc/firmware/gdb-test/gdb_uart.c Normal file
View File

@@ -0,0 +1,23 @@
#include "soc-hw.h"
/* Write a single character to debug host */
void
_gdb_write_char (char c)
{
uart_putchar(c);
}
/* Read and return a single character from debug host */
char
_gdb_read_char (void)
{
return uart_getchar();
}
/* Acknowledge specified interrupt that caused CPU to enter debug mode */
void
_gdb_ack_interrupt (void)
{
/* ACK interrupt */
/*__asm__ ("wcsr\tIA, %0" : : "d" (1 << interrupt));*/
}

5
lm32/logic/sakc/firmware/gdb-test/gdb_uart.h Normal file
View File

@@ -0,0 +1,5 @@
void _gdb_write_char (char c);
char _gdb_read_char (void);
void _gdb_ack_interrupt (void) ;

67
lm32/logic/sakc/firmware/gdb-test/linker.ld Normal file
View File

@@ -0,0 +1,67 @@
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
__DYNAMIC = 0;
_RAM_START = 0x40000000;
_RAM_SIZE = 0x100000;
_RAM_END = _RAM_START + _RAM_SIZE;
MEMORY {
ram : ORIGIN = 0x40000000, LENGTH = 0x100000 /* 1M */
}
SECTIONS
{
.boot :
{
_fboot = .;
*(.boot)
_eboot = .;
} > ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

20
lm32/logic/sakc/firmware/gdb-test/main.c Normal file
View File

@@ -0,0 +1,20 @@
#include "soc-hw.h"
void main()
{
gpio0->oe = 0x000000ff;
for(;;) {
int i;
for(i=0; i<8; i++) {
uint32_t out1, out2;
out1 = 0x01 << i;
out2 = 0x80 >> i;
gpio0->out = out1 | out2;
msleep(100);
}
}
}

133
lm32/logic/sakc/firmware/gdb-test/soc-hw.c Normal file
View File

@@ -0,0 +1,133 @@
#include "soc-hw.h"
uart_t *uart0 = (uart_t *) 0xf0000000;
timer_t *timer0 = (timer_t *) 0xf0010000;
gpio_t *gpio0 = (gpio_t *) 0xF0020000;
isr_ptr_t isr_table[32];
void tic_isr();
/***************************************************************************
* IRQ handling
*/
void isr_null()
{
}
void irq_handler(uint32_t pending)
{
int i;
for(i=0; i<32; i++) {
if (pending & 0x01) (*isr_table[i])();
pending >>= 1;
}
}
void isr_init()
{
int i;
for(i=0; i<32; i++)
isr_table[i] = &isr_null;
}
void isr_register(int irq, isr_ptr_t isr)
{
isr_table[irq] = isr;
}
void isr_unregister(int irq)
{
isr_table[irq] = &isr_null;
}
/***************************************************************************
* TIMER Functions
*/
void msleep(uint32_t msec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000)*msec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
do {
//halt();
tcr = timer0->tcr1;
} while ( ! (tcr & TIMER_TRIG) );
}
void nsleep(uint32_t nsec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000000)*nsec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
do {
//halt();
tcr = timer0->tcr1;
} while ( ! (tcr & TIMER_TRIG) );
}
uint32_t tic_msec;
void tic_isr()
{
tic_msec++;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
}
void tic_init()
{
tic_msec = 0;
// Setup timer0.0
timer0->compare0 = (FCPU/10000);
timer0->counter0 = 0;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
isr_register(1, &tic_isr);
}
/***************************************************************************
* UART Functions
*/
void uart_init()
{
//uart0->ier = 0x00; // Interrupt Enable Register
//uart0->lcr = 0x03; // Line Control Register: 8N1
//uart0->mcr = 0x00; // Modem Control Register
// Setup Divisor register (Fclk / Baud)
//uart0->div = (FCPU/(57600*16));
}
char uart_getchar()
{
while (! (uart0->ucr & UART_DR)) ;
return uart0->rxtx;
}
void uart_putchar(char c)
{
while (uart0->ucr & UART_BUSY) ;
uart0->rxtx = c;
}
void uart_putstr(char *str)
{
char *c = str;
while(*c) {
uart_putchar(*c);
c++;
}
}

108
lm32/logic/sakc/firmware/gdb-test/soc-hw.h Normal file
View File

@@ -0,0 +1,108 @@
#ifndef SPIKEHW_H
#define SPIKEHW_H
#define PROMSTART 0x00000000
#define RAMSTART 0x00000800
#define RAMSIZE 0x400
#define RAMEND (RAMSTART + RAMSIZE)
#define RAM_START 0x40000000
#define RAM_SIZE 0x04000000
#define FCPU 50000000
#define UART_RXBUFSIZE 32
/****************************************************************************
* Types
*/
typedef unsigned int uint32_t; // 32 Bit
typedef signed int int32_t; // 32 Bit
typedef unsigned char uint8_t; // 8 Bit
typedef signed char int8_t; // 8 Bit
/****************************************************************************
* Interrupt handling
*/
typedef void(*isr_ptr_t)(void);
void irq_enable();
void irq_disable();
void irq_set_mask(uint32_t mask);
uint32_t irq_get_mak();
void isr_init();
void isr_register(int irq, isr_ptr_t isr);
void isr_unregister(int irq);
/****************************************************************************
* General Stuff
*/
void halt();
void jump(uint32_t addr);
/****************************************************************************
* Timer
*/
#define TIMER_EN 0x08 // Enable Timer
#define TIMER_AR 0x04 // Auto-Reload
#define TIMER_IRQEN 0x02 // IRQ Enable
#define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR)
typedef struct {
volatile uint32_t tcr0;
volatile uint32_t compare0;
volatile uint32_t counter0;
volatile uint32_t tcr1;
volatile uint32_t compare1;
volatile uint32_t counter1;
} timer_t;
void msleep(uint32_t msec);
void nsleep(uint32_t nsec);
void tic_init();
/***************************************************************************
* GPIO0
*/
typedef struct {
volatile uint32_t ctrl;
volatile uint32_t dummy1;
volatile uint32_t dummy2;
volatile uint32_t dummy3;
volatile uint32_t in;
volatile uint32_t out;
volatile uint32_t oe;
} gpio_t;
/***************************************************************************
* UART0
*/
#define UART_DR 0x01 // RX Data Ready
#define UART_ERR 0x02 // RX Error
#define UART_BUSY 0x10 // TX Busy
typedef struct {
volatile uint32_t ucr;
volatile uint32_t rxtx;
} uart_t;
void uart_init();
void uart_putchar(char c);
void uart_putstr(char *str);
char uart_getchar();
/***************************************************************************
* Pointer to actual components
*/
extern timer_t *timer0;
extern uart_t *uart0;
extern gpio_t *gpio0;
extern uint32_t *sram0;
#endif // SPIKEHW_H

6
lm32/logic/sakc/firmware/gdb-test/start-gdb Normal file
View File

@@ -0,0 +1,6 @@
#!/bin/sh
lm32-elf-gdb image << ENDL
target remote /dev/ttyUSB0
ENDL