mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Adding lm32 demo to SAKC project
This commit is contained in:
Carlos Camargo
46
lm32/logic/sakc/firmware/hw-test/Makefile
Normal file
46
lm32/logic/sakc/firmware/hw-test/Makefile
Normal file
@@ -0,0 +1,46 @@
|
||||
LM32_CC=lm32-elf-gcc
|
||||
LM32_LD=lm32-elf-ld
|
||||
LM32_OBJCOPY=lm32-elf-objcopy
|
||||
LM32_OBJDUMP=lm32-elf-objdump
|
||||
|
||||
SREC2VRAM ?= ../../tools/srec2vram/srec2vram
|
||||
VRAMFILE=image.ram
|
||||
|
||||
CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
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||||
LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
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||||
SEGMENTS = -j .text -j .rodata -j .data
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||||
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all: image.srec $(VRAMFILE)
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||||
|
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crt0ram.o: crt0ram.S
|
||||
$(LM32_CC) $(CFLAGS) -c crt0ram.S
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||||
|
||||
main.o: main.c
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||||
$(LM32_CC) $(CFLAGS) -c main.c
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|
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soc-hw.o: soc-hw.c
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$(LM32_CC) $(CFLAGS) -c soc-hw.c
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|
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image: crt0ram.o main.o soc-hw.o linker.ld Makefile
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$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o soc-hw.o
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|
||||
image.lst: image
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||||
$(LM32_OBJDUMP) -h -S $< > $@
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||||
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||||
image.bin: image
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||||
$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
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||||
|
||||
image.srec: image image.lst
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||||
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
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||||
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$(VRAMFILE): image.srec
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$(SREC2VRAM) image.srec 0x40000000 0x1000 > $(VRAMFILE)
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clean:
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rm -f image image.lst image.bin image.srec image.map *.o *.d
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||||
|
||||
DEPS := $(wildcard *.d)
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||||
ifneq ($(DEPS),)
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include $(DEPS)
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||||
endif
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||||
|
||||
249
lm32/logic/sakc/firmware/hw-test/crt0ram.S
Normal file
249
lm32/logic/sakc/firmware/hw-test/crt0ram.S
Normal file
@@ -0,0 +1,249 @@
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||||
/*
|
||||
* LatticeMico32 C startup code.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
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||||
|
||||
/* Exception handlers - Must be 32 bytes long. */
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.section .text, "ax", @progbits
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.global _start
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.global irq_enable, irq_disable, irq_set_mask, irq_get_mask
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.global jump, halt
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.global get_sp, get_gp
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|
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_start:
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_reset_handler:
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xor r0, r0, r0
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||||
wcsr IE, r0
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||||
mvhi r1, hi(_reset_handler)
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||||
ori r1, r1, lo(_reset_handler)
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wcsr EBA, r1
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calli _crt0
|
||||
nop
|
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nop
|
||||
|
||||
_breakpoint_handler:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_ibuserror_handler:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_watchpoint_handler:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_dbuserror_handler:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_divzero_handler:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_interrupt_handler:
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sw (sp+0), ra
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calli _save_all
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rcsr r1, IP
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calli irq_handler
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mvhi r1, 0xffff
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ori r1, r1, 0xffff
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wcsr IP, r1
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bi _restore_all_and_eret
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||||
|
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_scall_handler:
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||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
_crt0:
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/* Setup stack and global pointer */
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mvhi sp, hi(_fstack)
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ori sp, sp, lo(_fstack)
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mvhi gp, hi(_gp)
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ori gp, gp, lo(_gp)
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/* Clear BSS */
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mvhi r1, hi(_fbss)
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ori r1, r1, lo(_fbss)
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mvhi r3, hi(_ebss)
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ori r3, r3, lo(_ebss)
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.clearBSS:
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be r1, r3, .callMain
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sw (r1+0), r0
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addi r1, r1, 4
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bi .clearBSS
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.callMain:
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mvi r1, 0
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mvi r2, 0
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mvi r3, 0
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calli main
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|
||||
irq_enable:
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||||
mvi r1, 1
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||||
wcsr IE, r1
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ret
|
||||
|
||||
irq_disable:
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||||
mvi r1, 0
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||||
wcsr IE, r1
|
||||
ret
|
||||
|
||||
irq_set_mask:
|
||||
wcsr IM, r1
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||||
ret
|
||||
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||||
irq_get_mask:
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||||
rcsr r1, IM
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||||
ret
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||||
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||||
jump:
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b r1
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||||
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||||
halt:
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bi halt
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||||
|
||||
/* Save all registers onto the stack */
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||||
_save_all:
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addi sp, sp, -128
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sw (sp+4), r1
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||||
sw (sp+8), r2
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||||
sw (sp+12), r3
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||||
sw (sp+16), r4
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||||
sw (sp+20), r5
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||||
sw (sp+24), r6
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||||
sw (sp+28), r7
|
||||
sw (sp+32), r8
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||||
sw (sp+36), r9
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||||
sw (sp+40), r10
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||||
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
|
||||
sw (sp+44), r11
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||||
sw (sp+48), r12
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||||
sw (sp+52), r13
|
||||
sw (sp+56), r14
|
||||
sw (sp+60), r15
|
||||
sw (sp+64), r16
|
||||
sw (sp+68), r17
|
||||
sw (sp+72), r18
|
||||
sw (sp+76), r19
|
||||
sw (sp+80), r20
|
||||
sw (sp+84), r21
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||||
sw (sp+88), r22
|
||||
sw (sp+92), r23
|
||||
sw (sp+96), r24
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||||
sw (sp+100), r25
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||||
sw (sp+104), r26
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sw (sp+108), r27
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#endif
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sw (sp+120), ea
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sw (sp+124), ba
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||||
/* ra and sp need special handling, as they have been modified */
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||||
lw r1, (sp+128)
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sw (sp+116), r1
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mv r1, sp
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addi r1, r1, 128
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sw (sp+112), r1
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ret
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||||
|
||||
/* Restore all registers and return from exception */
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_restore_all_and_eret:
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lw r1, (sp+4)
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lw r2, (sp+8)
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lw r3, (sp+12)
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lw r4, (sp+16)
|
||||
lw r5, (sp+20)
|
||||
lw r6, (sp+24)
|
||||
lw r7, (sp+28)
|
||||
lw r8, (sp+32)
|
||||
lw r9, (sp+36)
|
||||
lw r10, (sp+40)
|
||||
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
|
||||
lw r11, (sp+44)
|
||||
lw r12, (sp+48)
|
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lw r13, (sp+52)
|
||||
lw r14, (sp+56)
|
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lw r15, (sp+60)
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lw r16, (sp+64)
|
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lw r17, (sp+68)
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lw r18, (sp+72)
|
||||
lw r19, (sp+76)
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lw r20, (sp+80)
|
||||
lw r21, (sp+84)
|
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lw r22, (sp+88)
|
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lw r23, (sp+92)
|
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lw r24, (sp+96)
|
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lw r25, (sp+100)
|
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lw r26, (sp+104)
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lw r27, (sp+108)
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#endif
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lw ra, (sp+116)
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lw ea, (sp+120)
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lw ba, (sp+124)
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||||
/* Stack pointer must be restored last, in case it has been updated */
|
||||
lw sp, (sp+112)
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||||
eret
|
||||
|
||||
get_sp:
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mv r1, sp
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ret
|
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|
||||
get_gp:
|
||||
mv r1, gp
|
||||
ret
|
||||
|
||||
59
lm32/logic/sakc/firmware/hw-test/linker.ld
Normal file
59
lm32/logic/sakc/firmware/hw-test/linker.ld
Normal file
@@ -0,0 +1,59 @@
|
||||
OUTPUT_FORMAT("elf32-lm32")
|
||||
ENTRY(_start)
|
||||
|
||||
__DYNAMIC = 0;
|
||||
|
||||
|
||||
_RAM_START = 0x40000000;
|
||||
_RAM_SIZE = 0x1000;
|
||||
_RAM_END = _RAM_START + _RAM_SIZE;
|
||||
|
||||
MEMORY {
|
||||
ram : ORIGIN = 0x40000000, LENGTH = 0x1000 /* 4k */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_ftext = .;
|
||||
*(.text .stub .text.* .gnu.linkonce.t.*)
|
||||
_etext = .;
|
||||
} > ram
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
_erodata = .;
|
||||
} > ram
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
_gp = ALIGN(16);
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
_edata = .;
|
||||
} > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > ram
|
||||
}
|
||||
|
||||
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
|
||||
151
lm32/logic/sakc/firmware/hw-test/main.c
Normal file
151
lm32/logic/sakc/firmware/hw-test/main.c
Normal file
@@ -0,0 +1,151 @@
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
#include "soc-hw.h"
|
||||
|
||||
inline void writeint(uint32_t val)
|
||||
{
|
||||
uint32_t i, digit;
|
||||
|
||||
for (i=0; i<8; i++) {
|
||||
digit = (val & 0xf0000000) >> 28;
|
||||
if (digit >= 0xA)
|
||||
uart_putchar('A'+digit-10);
|
||||
else
|
||||
uart_putchar('0'+digit);
|
||||
val <<= 4;
|
||||
}
|
||||
}
|
||||
|
||||
void test2() {
|
||||
uart_putchar('b');
|
||||
}
|
||||
|
||||
void test() {
|
||||
uart_putchar('a');
|
||||
test2();
|
||||
uart_putchar('c');
|
||||
}
|
||||
|
||||
char glob[] = "Global";
|
||||
|
||||
volatile uint32_t *p;
|
||||
volatile uint8_t *p2;
|
||||
|
||||
extern uint32_t tic_msec;
|
||||
|
||||
int main()
|
||||
{
|
||||
char test2[] = "Lokalerstr";
|
||||
char *str = test2;
|
||||
uint32_t i;
|
||||
|
||||
// for (i = 0; i < 4; i++)
|
||||
// test2[i] = 'l';
|
||||
// glob[0] = 'g';
|
||||
|
||||
// Initialize stuff
|
||||
uart_init();
|
||||
|
||||
// Say Hello!
|
||||
uart_putstr( "** Spike Test Firmware **\n" );
|
||||
|
||||
// Initialize TIC
|
||||
isr_init();
|
||||
tic_init();
|
||||
irq_set_mask( 0x00000002 );
|
||||
irq_enable();
|
||||
|
||||
// Say Hello!
|
||||
uart_putstr( "Timer Interrupt instelled.\n" );
|
||||
|
||||
// Do some trivial tests
|
||||
uart_putstr( "Subroutine-Return Test: " );
|
||||
test();
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Local-Pointer Test:" );
|
||||
for (;*str; str++) {
|
||||
uart_putchar(*str);
|
||||
}
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Global-Pointer Test:" );
|
||||
str = glob;
|
||||
for (;*str; str++) {
|
||||
uart_putchar(*str);
|
||||
}
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Stack Pointer : " );
|
||||
writeint(get_sp());
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Global Pointer: " );
|
||||
writeint(get_gp());
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Timer Test (1s): " );
|
||||
for(i=0; i<4; i++) {
|
||||
uart_putstr("tic...");
|
||||
msleep(1000);
|
||||
}
|
||||
uart_putchar('\n');
|
||||
|
||||
uart_putstr( "Timer Interrupt counter: " );
|
||||
writeint( tic_msec );
|
||||
uart_putchar('\n');
|
||||
|
||||
int val = tic_msec;
|
||||
uart_putstr( "Shift: " );
|
||||
writeint( val );
|
||||
uart_putstr(" <-> ");
|
||||
for(i=0; i<32; i++) {
|
||||
if (val & 0x80000000)
|
||||
uart_putchar( '1' );
|
||||
else
|
||||
uart_putchar( '0' );
|
||||
|
||||
val <<= 1;
|
||||
}
|
||||
uart_putstr("\r\n");
|
||||
|
||||
uart_putstr( "GPIO Test..." );
|
||||
gpio0->oe = 0x000000ff;
|
||||
for(;;) {
|
||||
for(i=0; i<8; i++) {
|
||||
uint32_t out1, out2;
|
||||
|
||||
out1 = 0x01 << i;
|
||||
out2 = 0x80 >> i;
|
||||
gpio0->out = out1 | out2;
|
||||
|
||||
msleep(100);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
uart_putstr( "Memory Dump: " );
|
||||
uint32_t *start = (uint32_t *)0x40000000;
|
||||
uint32_t *end = (uint32_t *)0x40000100;
|
||||
uint32_t *p;
|
||||
for (p=start; p<end; p++) {
|
||||
if (((uint32_t)p & 12) == 0) {
|
||||
uart_putstr("\r\n[");
|
||||
writeint((uint32_t) p);
|
||||
uart_putchar(']');
|
||||
}
|
||||
|
||||
uart_putchar(' ');
|
||||
writeint(*p);
|
||||
}
|
||||
*/
|
||||
|
||||
uart_putstr("Entering Echo Test...\n");
|
||||
while (1) {
|
||||
uart_putchar(uart_getchar());
|
||||
}
|
||||
}
|
||||
|
||||
133
lm32/logic/sakc/firmware/hw-test/soc-hw.c
Normal file
133
lm32/logic/sakc/firmware/hw-test/soc-hw.c
Normal file
@@ -0,0 +1,133 @@
|
||||
#include "soc-hw.h"
|
||||
|
||||
uart_t *uart0 = (uart_t *) 0xf0000000;
|
||||
timer_t *timer0 = (timer_t *) 0xf0010000;
|
||||
gpio_t *gpio0 = (gpio_t *) 0xF0020000;
|
||||
|
||||
isr_ptr_t isr_table[32];
|
||||
|
||||
|
||||
void tic_isr();
|
||||
/***************************************************************************
|
||||
* IRQ handling
|
||||
*/
|
||||
void isr_null()
|
||||
{
|
||||
}
|
||||
|
||||
void irq_handler(uint32_t pending)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0; i<32; i++) {
|
||||
if (pending & 0x01) (*isr_table[i])();
|
||||
pending >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
void isr_init()
|
||||
{
|
||||
int i;
|
||||
for(i=0; i<32; i++)
|
||||
isr_table[i] = &isr_null;
|
||||
}
|
||||
|
||||
void isr_register(int irq, isr_ptr_t isr)
|
||||
{
|
||||
isr_table[irq] = isr;
|
||||
}
|
||||
|
||||
void isr_unregister(int irq)
|
||||
{
|
||||
isr_table[irq] = &isr_null;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* TIMER Functions
|
||||
*/
|
||||
void msleep(uint32_t msec)
|
||||
{
|
||||
uint32_t tcr;
|
||||
|
||||
// Use timer0.1
|
||||
timer0->compare1 = (FCPU/1000)*msec;
|
||||
timer0->counter1 = 0;
|
||||
timer0->tcr1 = TIMER_EN;
|
||||
|
||||
do {
|
||||
//halt();
|
||||
tcr = timer0->tcr1;
|
||||
} while ( ! (tcr & TIMER_TRIG) );
|
||||
}
|
||||
|
||||
void nsleep(uint32_t nsec)
|
||||
{
|
||||
uint32_t tcr;
|
||||
|
||||
// Use timer0.1
|
||||
timer0->compare1 = (FCPU/1000000)*nsec;
|
||||
timer0->counter1 = 0;
|
||||
timer0->tcr1 = TIMER_EN;
|
||||
|
||||
do {
|
||||
//halt();
|
||||
tcr = timer0->tcr1;
|
||||
} while ( ! (tcr & TIMER_TRIG) );
|
||||
}
|
||||
|
||||
|
||||
uint32_t tic_msec;
|
||||
|
||||
void tic_isr()
|
||||
{
|
||||
tic_msec++;
|
||||
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
|
||||
}
|
||||
|
||||
void tic_init()
|
||||
{
|
||||
tic_msec = 0;
|
||||
|
||||
// Setup timer0.0
|
||||
timer0->compare0 = (FCPU/10000);
|
||||
timer0->counter0 = 0;
|
||||
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
|
||||
|
||||
isr_register(1, &tic_isr);
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* UART Functions
|
||||
*/
|
||||
void uart_init()
|
||||
{
|
||||
//uart0->ier = 0x00; // Interrupt Enable Register
|
||||
//uart0->lcr = 0x03; // Line Control Register: 8N1
|
||||
//uart0->mcr = 0x00; // Modem Control Register
|
||||
|
||||
// Setup Divisor register (Fclk / Baud)
|
||||
//uart0->div = (FCPU/(57600*16));
|
||||
}
|
||||
|
||||
char uart_getchar()
|
||||
{
|
||||
while (! (uart0->ucr & UART_DR)) ;
|
||||
return uart0->rxtx;
|
||||
}
|
||||
|
||||
void uart_putchar(char c)
|
||||
{
|
||||
while (uart0->ucr & UART_BUSY) ;
|
||||
uart0->rxtx = c;
|
||||
}
|
||||
|
||||
void uart_putstr(char *str)
|
||||
{
|
||||
char *c = str;
|
||||
while(*c) {
|
||||
uart_putchar(*c);
|
||||
c++;
|
||||
}
|
||||
}
|
||||
|
||||
108
lm32/logic/sakc/firmware/hw-test/soc-hw.h
Normal file
108
lm32/logic/sakc/firmware/hw-test/soc-hw.h
Normal file
@@ -0,0 +1,108 @@
|
||||
#ifndef SPIKEHW_H
|
||||
#define SPIKEHW_H
|
||||
|
||||
#define PROMSTART 0x00000000
|
||||
#define RAMSTART 0x00000800
|
||||
#define RAMSIZE 0x400
|
||||
#define RAMEND (RAMSTART + RAMSIZE)
|
||||
|
||||
#define RAM_START 0x40000000
|
||||
#define RAM_SIZE 0x04000000
|
||||
|
||||
#define FCPU 50000000
|
||||
|
||||
#define UART_RXBUFSIZE 32
|
||||
|
||||
/****************************************************************************
|
||||
* Types
|
||||
*/
|
||||
typedef unsigned int uint32_t; // 32 Bit
|
||||
typedef signed int int32_t; // 32 Bit
|
||||
|
||||
typedef unsigned char uint8_t; // 8 Bit
|
||||
typedef signed char int8_t; // 8 Bit
|
||||
|
||||
/****************************************************************************
|
||||
* Interrupt handling
|
||||
*/
|
||||
typedef void(*isr_ptr_t)(void);
|
||||
|
||||
void irq_enable();
|
||||
void irq_disable();
|
||||
void irq_set_mask(uint32_t mask);
|
||||
uint32_t irq_get_mak();
|
||||
|
||||
void isr_init();
|
||||
void isr_register(int irq, isr_ptr_t isr);
|
||||
void isr_unregister(int irq);
|
||||
|
||||
/****************************************************************************
|
||||
* General Stuff
|
||||
*/
|
||||
void halt();
|
||||
void jump(uint32_t addr);
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Timer
|
||||
*/
|
||||
#define TIMER_EN 0x08 // Enable Timer
|
||||
#define TIMER_AR 0x04 // Auto-Reload
|
||||
#define TIMER_IRQEN 0x02 // IRQ Enable
|
||||
#define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR)
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t tcr0;
|
||||
volatile uint32_t compare0;
|
||||
volatile uint32_t counter0;
|
||||
volatile uint32_t tcr1;
|
||||
volatile uint32_t compare1;
|
||||
volatile uint32_t counter1;
|
||||
} timer_t;
|
||||
|
||||
void msleep(uint32_t msec);
|
||||
void nsleep(uint32_t nsec);
|
||||
|
||||
void tic_init();
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* GPIO0
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t ctrl;
|
||||
volatile uint32_t dummy1;
|
||||
volatile uint32_t dummy2;
|
||||
volatile uint32_t dummy3;
|
||||
volatile uint32_t in;
|
||||
volatile uint32_t out;
|
||||
volatile uint32_t oe;
|
||||
} gpio_t;
|
||||
|
||||
/***************************************************************************
|
||||
* UART0
|
||||
*/
|
||||
#define UART_DR 0x01 // RX Data Ready
|
||||
#define UART_ERR 0x02 // RX Error
|
||||
#define UART_BUSY 0x10 // TX Busy
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t ucr;
|
||||
volatile uint32_t rxtx;
|
||||
} uart_t;
|
||||
|
||||
void uart_init();
|
||||
void uart_putchar(char c);
|
||||
void uart_putstr(char *str);
|
||||
char uart_getchar();
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Pointer to actual components
|
||||
*/
|
||||
extern timer_t *timer0;
|
||||
extern uart_t *uart0;
|
||||
extern gpio_t *gpio0;
|
||||
extern uint32_t *sram0;
|
||||
|
||||
#endif // SPIKEHW_H
|
||||
Reference in New Issue
Block a user