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Adding lm32 demo to SAKC project

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This commit is contained in:
Carlos Camargo
2010-05-25 21:49:58 -05:00
parent 26b0c73a84
commit 61d4408f2a
145 changed files with 27924 additions and 1501 deletions
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1379
lm32/logic/sakc/sim/ddr/ddr.v Normal file
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/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
// `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.45; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
// Size Parameters based on Part Width
//`else `define x16
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter full_mem_bits = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
parameter part_mem_bits = 14; // Set this parameter to control how many unique addresses are used
parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors
parameter Debug = 1; // Turn on debug message

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: mig_v1_73_b0 $
// \ \ Application : MIG
// / / Filename : mem_interface_top_parameters_0.v
// /___/ /\ Date Last Modified : $Date: 2007/06/06 05:44:42 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3E/3A
// Design Name : DDR1 SDRAM
// Purpose : This module has the parameters used in the design.
///////////////////////////////////////////////////////////////////////////////
`define data_width 16
`define data_strobe_width 2
`define data_mask_width 2
`define clk_width 1
`define fifo_16 1
`define ReadEnable 1
`define memory_width 8
`define DatabitsPerReadClock 8
`define DatabitsPerMask 8
`define no_of_cs 1
`define data_mask 1
`define mask_disable 0
`define RESET 0
`define cke_width 1
`define registered 0
`define col_ap_width 11
`define write_pipe_itr 1
`define write_pipeline 4
`define top_bottom 0
`define left_right 1
`define row_address 13
`define column_address 10
`define bank_address 2
`define spartan3e 1
`define burst_length 3'b001
`define burst_type 1'b0
`define cas_latency_value 3'b110
`define Operating_mode 5'b00000
`define load_mode_register 13'b0000001100001
`define drive_strengh 1'b0
`define dll_enable 1'b0
`define ext_load_mode_register 13'b0000000000000
`define chip_address 1
`define reset_active_low 1'b1
`define rcd_count_value 3'b001
`define ras_count_value 4'b0101
`define mrd_count_value 1'b0
`define rp_count_value 3'b001
`define rfc_count_value 6'b001001
`define twr_count_value 3'b110
`define twtr_count_value 3'b100
`define max_ref_width 11
`define max_ref_cnt 11'b10000000001
`timescale 1ns/100ps

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********************************************************************************************
The sim folder has sample test_bench files to simulate the designs in Modelsim environment.
This folder has the memory model, test bench, glbl file and required parameter files.
Read the steps in this file before simulations are done.
To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI
options.
Data_width : 64
HDL : Verilog or VHDL
Memory configuration : x16
DIMM/Component : Component
Memory Part No : MT46V16M16XX-5
Add test bench : Yes
Use DCM : Yes
Number of controllers : 1
Number of Write pipelines : 4
-----------------------------------------------For Verilog or VHDL----------------------------------------------------------
1. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder
to the project Also add the memory model, test bench and glbl files from the sim folder.
2. Compile the design.
3. After successful compilation of design load the design using the following comamnd.
vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
Note : User should set proper path for unisim verilog libraries
4. After the design is successfully loaded, run the simulations and view the waveforms.
Notes :
1. To run simulations for different data widths and configurations, users should modify the test bench files
with right memory models and design files.
2. User must manually change the frequency of the test bench for proper simulations.
3. Users should modify the test bench files for without test bench case.

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//---------------------------------------------------------------------------
// Behavioral model of a static ram chip
//
// Organization:
//
// 16 bit x 2**(adr_width-1)
//---------------------------------------------------------------------------
module sram16 #(
parameter adr_width = 18
) (
input [adr_width-1:0] adr,
inout [15:0] dat,
input ub_n,
input lb_n,
input cs_n,
input we_n,
input oe_n
);
parameter dat_width = 16;
//---------------------------------------------------------------------------
// Actual RAM cells
//---------------------------------------------------------------------------
reg [7:0] mem_ub [0:1<<adr_width];
reg [7:0] mem_lb [0:1<<adr_width];
//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
wire [15:0] mem = { mem_ub[adr], mem_lb[adr] };
wire [15:0] zzz = 16'bz;
// Drive output
assign dat = (!cs_n && !oe_n) ? mem : zzz;
// Write to UB
always @(*)
if (!cs_n && !we_n && !ub_n)
mem_ub[adr] = dat[15:8];
// Write to LB
always @(*)
if (!cs_n && !we_n && !lb_n)
mem_lb[adr] = dat[7:0];
always @(*)
if (!we_n && !oe_n)
$display("Operational error in RamChip: OE and WE both active");
endmodule

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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5.158.1 2007/03/09 18:13:02 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Global Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// End Revision
`timescale 100 ps / 10 ps
module BUFG (O, I);
output O;
input I;
buf B1 (O, I);
endmodule

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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.27)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
// /___/ /\ Filename : FDDRRSE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678)
// 10/20/05 - Add set & reset check to main block. (CR219794)
// 10/28/05 - combine strobe block and data block. (CR220298).
// 2/07/06 - Remove set & reset from main block and add specify block (CR225119)
// 2/10/06 - Change Q from reg to wire (CR 225613)
// End Revision
`timescale 1 ps / 1 ps
module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
parameter INIT = 1'h0;
output Q;
input C0, C1, CE, D0, D1, R, S;
wire Q;
reg q_out;
reg q0_out, q1_out;
reg C0_tmp, C1_tmp;
initial begin
q_out = INIT;
q0_out = INIT;
q1_out = INIT;
C0_tmp = 0;
C1_tmp = 0;
end
assign Q = q_out;
always @(posedge C0)
if (CE == 1 || R == 1 || S == 1) begin
C0_tmp <= 1;
C0_tmp <= #100 0;
end
always @(posedge C1)
if (CE == 1 || R == 1 || S == 1) begin
C1_tmp <= 1;
C1_tmp <= #100 0;
end
always @(posedge C0)
if (R)
q0_out <= 0;
else if (S)
q0_out <= 1;
else if (CE)
q0_out <= D0;
always @(posedge C1)
if (R)
q1_out <= 0;
else if (S)
q1_out <= 1;
else if (CE)
q1_out <= D1;
always @(posedge C0_tmp or posedge C1_tmp )
if (C1_tmp)
q_out = q1_out;
else
q_out = q0_out;
specify
if (R)
(posedge C0 => (Q +: 1'b0)) = (100, 100);
if (!R && S)
(posedge C0 => (Q +: 1'b1)) = (100, 100);
if (!R && !S && CE)
(posedge C0 => (Q +: D0)) = (100, 100);
if (R)
(posedge C1 => (Q +: 1'b0)) = (100, 100);
if (!R && S)
(posedge C1 => (Q +: 1'b1)) = (100, 100);
if (!R && !S && CE)
(posedge C1 => (Q +: D1)) = (100, 100);
endspecify
endmodule