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nn-usb-fpga
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Adding a simple plasma example read write char short int, adding simulations 

for this example
This commit is contained in:
Carlos Camargo 2010-04-30 22:21:55 -05:00
parent 0348078440
commit 622f59856f
16 changed files with 212 additions and 630 deletions
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2
Examples/blink/logic/simulation/blink_TB.do
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@ -1,7 +1,7 @@
vlib work
vlog +acc "../blink.v"
vlog +acc "../blink_TB.v"
vlog +acc "/opt/cad/Xilinx/verilog/src/glbl.v"
vlog +acc "glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver blink_TB_v glbl
view wave
do wave.do

2
plasma/Makefile
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@ -1,5 +1,5 @@
TARGET = bootldr
DIRS = tools bootldr logic
DIRS = tools bootldr logic gpio
all:
for n in $(DIRS); do $(MAKE) -C $$n || exit 1; done

2
plasma/bootldr/bootldr.c
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@ -122,7 +122,7 @@ int main(void)
DdrInit(); //Harmless if SDRAM instead of DDR
puts("\nGreetings from the bootloader ");
puts("\n1233456Greetings from the bootloader ");
puts(__DATE__);
puts(" ");
puts(__TIME__);

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43
plasma/gpio/Makefile Normal file
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@ -0,0 +1,43 @@
VHDL_DIR = ../logic
TOOLS_DIR = ../bin
LIB_DIR = ../lib
TARGET = gpio
CROSS = mips-elf
GCC = $(CROSS)-gcc
AS = $(CROSS)-as
LD = $(CROSS)-ld
DUMP = $(CROSS)-objdump
OBJCOPY = $(CROSS)-objcopy
INC_PATH = ../include
CFLAGS = -O2 -I$(INC_PATH) -Wall -c -s
ILDFLAGS = -Ttext 0 -eentry -Map $@.map -s -N
LDFLAGS = -Ttext 0x10000000 -eentry -Map $@.map -s -N
#Internal RAM 0x00
#External RAM 0x10000000
vpath %.c $(LIB_DIR)
vpath %.S $(LIB_DIR)
.c.o:
$(GCC) $(CFLAGS) $<
.S.o:
$(AS) -o $@ $<
all: $(TARGET)
clean:
-rm -rf *.o *.txt *.map *.lst *.bin opcodes_iram opcodes_ram test bootldr $(TARGET)
$(TARGET): crt0.o $(TARGET).o no_os.o ddr_init.o
$(LD) $(ILDFLAGS) -o $@ $^
$(OBJCOPY) -I elf32-big -O binary $@ $@.bin
vhdl_mem: $(TARGET)
$(TOOLS_DIR)/ramimage $(VHDL_DIR)/ram_xilinx.vhd $^.bin $(VHDL_DIR)/ram_image.vhd
upload: $(TARGET)
sudo cat $^.bin > /dev/ttyUSB0
run: $(TARGET)
$(TOOLS_DIR)/mlite $^.bin

61
plasma/gpio/gpio.c Normal file
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@ -0,0 +1,61 @@
#include "plasma.h"
#define MemoryRead(A) (*(volatile unsigned long*)(A))
#define MemoryWrite(A,V) *(volatile unsigned long*)(A)=(V)
typedef unsigned long uint32;
typedef unsigned short uint16;
int main(void)
{
volatile unsigned char *data8;
volatile unsigned short *data16;
volatile unsigned int *data32;
unsigned char test8;
unsigned short test16;
unsigned int test32, tmp;
data8 = (unsigned char *)(0x20001000);
data16 = (unsigned short *)(0x20002000);
data32 = (unsigned int *)(0x20003000);
*data8 = 0x10;
data8++;
*data8 = 0x11;
data8++;
*data8 = 0x12;
data8++;
*data8 = 0x13;
data8++;
*data8 = 0x14;
*data16 = 0x2020;
data16++;
*data16 = 0x2121;
data16++;
*data16 = 0x2222;
data16++;
*data32 = 0x30303030;
test8 = *data8;
test16 = *data16;
test32 = *data32;
data8 += 4;
data16++;
data32++;
test8 = *data8;
test16 = *data16;
test32 = *data32;
tmp = test8 + test16 + test32;
*data32 = 0xAAAAAAAA;
return 0;
}

6
plasma/logic/Makefile
View File

@ -1,4 +1,4 @@
DESIGN = plasma_3e
DESIGN = plasma
PINS = $(DESIGN).ucf
DEVICE = xc3s500e-fg320-4
BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
@ -11,9 +11,6 @@ SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd plasma_3e.vhd ram_image.vhd
all: bits
@ -22,6 +19,7 @@ remake: clean-build all
clean:
rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
rm -rf *.bit rm -rf simulation/work simulation/*wlf
rm -rf simulation/transcript
clean-build:
rm -rf build

3
plasma/logic/mlite_pack.vhd
View File

@ -415,7 +415,6 @@ package mlite_pack is
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
@ -427,8 +426,6 @@ package mlite_pack is
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));

81
plasma/logic/plasma.vhd
View File

@ -21,12 +21,9 @@
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
@ -39,7 +36,6 @@ use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
@ -51,10 +47,7 @@ entity plasma is
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma
@ -69,16 +62,13 @@ architecture logic of plasma is
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal write_enable : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
@ -86,8 +76,6 @@ architecture logic of plasma is
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
@ -98,29 +86,23 @@ architecture logic of plasma is
signal cache_check : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --DDR in use
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
mem_busy <= mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
-- cache_miss or --Cache wait
-- (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
-- gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
-- gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
@ -161,11 +143,7 @@ begin --architecture
cache_check => cache_check, --Stage1: address_next in first 2MB DDR
cache_checking => cache_checking, --Stage2
cache_miss => cache_miss); --Stage3
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
end generate; --opt_cache2
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, data_read, data_read_uart, cpu_pause,
@ -225,8 +203,7 @@ begin --architecture
end if;
end process;
ram_enable <= '1' when address_next(30 downto 28) = "000" or
cache_check = '1' or cache_miss = '1' else '0';
ram_enable <= '1' when address_next(30 downto 28) = "000" or cache_check = '1' or cache_miss = '1' else '0';
ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
ram_address(31 downto 13) <= ZERO(31 downto 13);
ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
@ -258,44 +235,10 @@ begin --architecture
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
end; --architecture logic

182
plasma/logic/ram_image.vhd
View File

@ -45,27 +45,27 @@ INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"1c24001030008c24ac24ac9424003c00180003241c24a4248c0018ac2400003c",
INIT_05 => X"a00024241028302400a03c24243c3c0003001030008cacac242400003c000300",
INIT_06 => X"100010000c00102a0200260c24af08af2424240000afafafafaf270103001424",
INIT_07 => X"240c001a001427038f8f8f8f8f8f8f02240c240c000824102c24142c24142e24",
INIT_08 => X"3c240c3c240c3c240c3c240c3caf0cafafafafafafafafaf270008260c24240c",
INIT_09 => X"3c3c3c3c3c3c003c3c0c003c240c3c3c1430248c3c1030008c34ac3c3c24240c",
INIT_0A => X"0c3c240c3c270c260c260c260c260c240c3c240c3c240c3c240c3c240c3c240c",
INIT_0B => X"3c3c08240c3c000c000c8e0000008c0024003c3c102c260000142c2400000c24",
INIT_0C => X"3c3c080002a208000c000c00000c240c3c0008923c08ae000c000c00000c240c",
INIT_0D => X"080216a002260c00000010000c240c3c3c080216260c900200000010000c240c",
INIT_0E => X"0010000c240c3c3c08240c000c000c0014002490020000000010000c240c3c3c",
INIT_0F => X"240c3c021402240c000c260c8c021032021002240c000c260c8c02240c3c0000",
INIT_10 => X"14343c000c240c3c3c0800003c0016260c262610000c3c120008a23c243c3c08",
INIT_11 => X"0c000c2608240c3c000c020c240c3c00000c240c3c020c3c083c0c003c000c00",
INIT_12 => X"00100082260c00240800100080afafaf270003ac001030008c343c3c08240c00",
INIT_13 => X"2424142c3002242400afafafaf272703008f8f8f00140082000c2682000c2414",
INIT_14 => X"24243c3c2703008f8c3c10000caf2730038c343c240827038f8f8f8f0216260c",
INIT_15 => X"740a00616d20423a003230303241656c62747267650a24038c0014ac00248c3c",
INIT_16 => X"617965330a7769796532006f61796531006e706e724f303030206e6569612020",
INIT_17 => X"4600753900736838006979656137617965613673647475350a62697965340079",
INIT_18 => X"37336820660a0d786e6e0a786e750a3d6541206820720a3e00616f446f42316f",
INIT_04 => X"913434ada5342434343ca5a5242434a134a1242434a034a024243434a024343c",
INIT_05 => X"240800100080afafaf270003ac001030008c343c0003ac8c34943c908d349434",
INIT_06 => X"2400afafafaf272703008f8f8f00140082000c2682000c241400100082260c00",
INIT_07 => X"8f8c3c10000caf2730038c343c240827038f8f8f8f0216260c2424142c300224",
INIT_08 => X"00000000000000000000000000000024038c0014ac00248c3c24243c3c270300",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -122,28 +122,28 @@ INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"c0c60040420062636284658205620205c000e084c0a582c6a200c0a202a20502",
INIT_05 => X"c2e5070740a285634040036642020300e000404200828283020382040200e000",
INIT_06 => X"54405300000040220312310090b000bf1514130000b1b2b3b4b5bd00e004c3c6",
INIT_07 => X"040000208095bde0b0b1b2b3b4b5bf4004000400000090404282404282400250",
INIT_08 => X"04840004840004840004840004b000b1b2b3b4b5b6b7bebfbd12003100040400",
INIT_09 => X"021e171615144002060000048400041543420382146063004342830204038400",
INIT_0A => X"0002440002c400e400c400a40084004400024400024400024400024400024400",
INIT_0B => X"0202004400024000000044008000444383030402406203000040424240000044",
INIT_0C => X"0202000040500040004000400000440002000044020050400040004000004400",
INIT_0D => X"0000136251100000004040000044000202000011100044420000404000004400",
INIT_0E => X"404000004400020200040040000000a0a683a543420000004040000044000202",
INIT_0F => X"4400020060130400400030004450400200601304004000300044504400020000",
INIT_10 => X"4363030000440002020000400240535200101040000002110000501311120200",
INIT_11 => X"0000000300440002400040004400024000004400020000020006000004000000",
INIT_12 => X"00400002100040110080400082b1bfb0bd00e0a40040420062a3050200040040",
INIT_13 => X"646440624312111080bfb0b1b2bdbde000b0b1bf004000024000100200000451",
INIT_14 => X"63440302bde000bf6203400000bfbd42e06263030400bde0b0b1b2bf12111000",
INIT_15 => X"6957007320666f0a003a36313770726f6f686f73744742e0a200834045848205",
INIT_16 => X"64206d2e006f74206d2e007264206d2e007374752074303078616b206d726266",
INIT_17 => X"2e006d2e0075652e0074206d772e64206d772e73646f6d2e007974206d2e0074",
INIT_18 => X"3834207769430a3e2074433e206556207364006569654120007320526d203270",
INIT_19 => X"0004000080240080000000000000000000000000000000000000000000000000",
INIT_04 => X"868283a26342038b8d02422302038a828903020388e28cc302038786a2028504",
INIT_05 => X"110080400082b1bfb0bd00e0a40040420062a30500e0a2a342860262a6844785",
INIT_06 => X"1080bfb0b1b2bdbde000b0b1bf00400002400010020000045100400002100040",
INIT_07 => X"bf6203400000bfbd42e06263030400bde0b0b1b2bf1211100064644062431211",
INIT_08 => X"00000000000000040000802400800042e0a20083404584820563440302bde000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -195,32 +195,32 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000100ff18000e000f000c008c00",
INIT_01 => X"000000000000000000000000000000000000022000002000d800d800ff700000",
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
INIT_01 => X"000000000000000000000000000000000000002000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"ffff00ff00000000000000000018301800000000ff0000ff0000000000282830",
INIT_05 => X"001000000000000c4000000d0d0000000000ff00000000000000202030000000",
INIT_06 => X"002000000200000090190002ff00000000000088900000000000ff100021ffff",
INIT_07 => X"0002000080ff00000000000000000010000200020000ff0000ffff00ffff00ff",
INIT_08 => X"000a02000c02000a02000a02000002000000000000000000ff9100ff02000002",
INIT_09 => X"000000000000f810000028100a02000000ff3c00000000000000002030000a02",
INIT_0A => X"02000b02000b020b020b020b020b020b02000b02000b02000b02000b02000a02",
INIT_0B => X"0000010b0200200200000000000000100c100000ff00ff90000000ff8000020c",
INIT_0C => X"00000100f80001200280002000000c0200000100000100200280002000000c02",
INIT_0D => X"0188ff00180002888098ff00000c0200000110ff00020010108088ff00000c02",
INIT_0E => X"980000000c0200000100022002000010ff20000010102028300000000c020000",
INIT_0F => X"0c020088ff180002200200000010ff0088001800022002000000100c02008880",
INIT_10 => X"ff561200000c0200000100f81080ff0002ff00ff000210008002001027100001",
INIT_11 => X"022000ff010b0200200220000c02009000000c02002002000100002810200000",
INIT_12 => X"00000000000220000280000000000000ff00000010ff00000000200001000220",
INIT_13 => X"000000000010ff009000000000ff00001000000000ff000020020000000200ff",
INIT_14 => X"0c0c0000000000000020ff000200ff0000000020000200000000000010ffff02",
INIT_15 => X"6e61006866726f0000333a30207220616f656d20697200000000ff0010000010",
INIT_16 => X"20726f20007265776f20006420726f20003a69204d680a303174656c6179696f",
INIT_17 => X"20007020006d63200065776f20200a726f20200a72207020007465776f200065",
INIT_18 => X"3e353169726f002068206f2068206100736400786e7364000068662020663879",
INIT_19 => X"0020000000202800000804040404040404040408040407070606060606050500",
INIT_04 => X"0020100000302220303000002120200020000000100010000000101000001020",
INIT_05 => X"000080000000000000ff00000010ff000000002010000000aa00aa0000200030",
INIT_06 => X"009000000000ff00001000000000ff000020000000000000ff00000000000020",
INIT_07 => X"000020ff000000ff0000000020000000000000000010ffff00000000000010ff",
INIT_08 => X"00000000000000200000002028000000000000ff001000001004040000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -272,32 +272,32 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e000704fd2a00f8001000fc00f001",
INIT_01 => X"504c4844403c3834302c2824201c181410008a2410200060125c1058fc005450",
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a005800700064006001",
INIT_01 => X"504c4844403c3834302c2824201c18141000f12410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"f4fe00fc80000004000200004021004011000802fb0400fe00000700ff214000",
INIT_05 => X"00213037020a0fff21080007000000000800fc8000000000d020214000000800",
INIT_06 => X"0c210e009100121021000145c910db28080d0a212114181c2024d0210802f7ff",
INIT_07 => X"0845000821d930081014181c202428210a450d4500d4a9111a9fed1abff10ad0",
INIT_08 => X"00d44f00344f00c84f00a84f00109c14181c2024282c3034c802d8ff45082045",
INIT_09 => X"000000000000090002802100e44f00000cff1c00001001000050000000ffe04f",
INIT_0A => X"4f00fc4f00f04fe04fc84fb44fa04f884f00704f00584f00404f00284f00f84f",
INIT_0B => X"0000406c4f00214f00b100000800002184800000d416cf2100c20ad021009120",
INIT_0C => X"0000400009003f214f21b12100c5444f00007600004000214f21b12100c5444f",
INIT_0D => X"4021fb002101912121218900c5544f00004021fb014500212121219a00c5544f",
INIT_0E => X"211e00c5544f0000400a45214f00b121fb21010021212121217600c5544f0000",
INIT_0F => X"644f0021f42b2045214f04b10021f00f210e2b2045214f04b10021644f002121",
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INIT_11 => X"4f21b1cf6a6c4f00214f21b1384f002100c5244f0021450040028f210021a300",
INIT_12 => X"000d00000145210a6021160000141810e000080021fc020000200000400a4521",
INIT_13 => X"5730020a0f06fc1c211c101418e020082110141800f500002145010000450df8",
INIT_14 => X"fcdc0000180800100000fd008c10e80108002000494520081014181c06f8fc45",
INIT_15 => X"6769000a6c6f74000030340032200064742020666e6584080000fb0021040000",
INIT_16 => X"6265724d00642072724d000a7765724d000a6f4f656500303020646967206e72",
INIT_17 => X"43000a44000a6b43000a72726d520065726d52006561204a00652072724d000a",
INIT_18 => X"203632746d6e00006569750065696c002072003e20736400000a6c7444724b20",
INIT_19 => X"00001010200000207060fcfcfcfcfcfcfcfcfc08fcfc6404c07c6c3c30fcd400",
INIT_04 => X"0006080000302204003000002120020000001413030004001211020100100000",
INIT_05 => X"0ac721160000141810e000080021fc020000200021080000aa00aa0000080004",
INIT_06 => X"1c211c101418e020082110141800f5000021ac010000ac0df8000d000001ac21",
INIT_07 => X"100000fd00f310e8010800200049ac20081014181c06f8fcac5730020a0f06fc",
INIT_08 => X"00000000000000001010200000207084080000fb002104000064440000180800",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",

29
plasma/logic/simulation/output.txt
View File

@ -1,29 +0,0 @@
Greetings from the bootloader Apr 21 2010 19:05:48:
Waiting for binary image linked at 0x10000000
Other Menu Options:
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash
>
Waiting for binary image linked at 0x10000000
Other Menu Options:
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash
> 4

29
plasma/logic/simulation/plasma_3e_TB.do
View File

@ -1,29 +0,0 @@
vlib work
vmap work
vcom -93 -work work ../mlite_pack.vhd
vcom -93 -work work ../plasma.vhd
vcom -93 -work work ../alu.vhd
vcom -93 -work work ../control.vhd
vcom -93 -work work ../mem_ctrl.vhd
vcom -93 -work work ../mult.vhd
vcom -93 -work work ../shifter.vhd
vcom -93 -work work ../bus_mux.vhd
vcom -93 -work work ../ddr_ctrl.vhd
vcom -93 -work work ../mlite_cpu.vhd
vcom -93 -work work ../pc_next.vhd
vcom -93 -work work ../cache.vhd
vcom -93 -work work ../eth_dma.vhd
vcom -93 -work work ../pipeline.vhd
vcom -93 -work work ../reg_bank.vhd
vcom -93 -work work ../uart.vhd
vcom -93 -work work ../plasma_3e.vhd
vcom -93 -work work ../ram_image.vhd
vcom -93 -work work ../tbench.vhd
vsim -t 1ps tbench
view wave
add wave *
view structure
view signals
run 15ms

283
plasma/logic/simulation/transcript
View File

@ -1,283 +0,0 @@
# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-21-generic
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do plasma_3e_TB.do
# Reading /home/opt/cad/modeltech/linux/../modelsim.ini
# "work" maps to directory work. (Default mapping)
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package mlite_pack
# -- Compiling package body mlite_pack
# -- Loading package mlite_pack
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity plasma
# -- Compiling architecture logic of plasma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity alu
# -- Compiling architecture logic of alu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity control
# -- Compiling architecture logic of control
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity mem_ctrl
# -- Compiling architecture logic of mem_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity mult
# -- Compiling architecture logic of mult
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity shifter
# -- Compiling architecture logic of shifter
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity bus_mux
# -- Compiling architecture logic of bus_mux
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity ddr_ctrl
# -- Compiling architecture logic of ddr_ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity mlite_cpu
# -- Compiling architecture logic of mlite_cpu
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pc_next
# -- Compiling architecture logic of pc_next
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package mlite_pack
# -- Compiling entity cache
# -- Compiling architecture logic of cache
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity eth_dma
# -- Compiling architecture logic of eth_dma
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Compiling entity pipeline
# -- Compiling architecture logic of pipeline
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity reg_bank
# -- Compiling architecture ram_block of reg_bank
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Compiling entity uart
# -- Compiling architecture logic of uart
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity plasma_3e
# -- Compiling architecture logic of plasma_3e
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package attributes
# -- Loading package std_logic_misc
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package mlite_pack
# -- Loading package vcomponents
# -- Compiling entity ram
# -- Compiling architecture logic of ram
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package mlite_pack
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity tbench
# -- Compiling architecture logic of tbench
# vsim -t 1ps tbench
# Loading /home/opt/cad/modeltech/linux/../std.standard
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_1164(body)
# Loading work.mlite_pack(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_arith(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_unsigned(body)
# Loading work.tbench(logic)
# Loading work.plasma(logic)
# Loading work.mlite_cpu(logic)
# Loading work.pc_next(logic)
# Loading work.mem_ctrl(logic)
# Loading work.control(logic)
# Loading work.reg_bank(ram_block)
# Loading work.bus_mux(logic)
# Loading work.alu(logic)
# Loading work.shifter(logic)
# Loading work.mult(logic)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vcomponents
# Loading work.cache(logic)
# Loading /home/opt/cad/modeltech/linux/../synopsys.attributes
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_misc(body)
# Loading work.ram(logic)
# Loading /home/opt/cad/modeltech/linux/../std.textio(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_timing(body)
# Loading /home/opt/cad/modeltech/linux/../ieee.vital_primitives(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vpkg(body)
# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.ramb16_s9(ramb16_s9_v)
# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_textio(body)
# Loading work.uart(logic)
# Loading work.eth_dma(logic)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u3_uart
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 1 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 2 Instance: /tbench
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/opt_cache2/u_cache
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
# Break key hit
# Simulation stop requested.

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---------------------------------------------------------------------
-- TITLE: Test Bench
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a test bench for testing the Plasma CPU core.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity tbench is
end; --entity tbench
architecture logic of tbench is
constant memory_type : string :=
"TRI_PORT_X";
-- "DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
constant log_file : string :=
-- "UNUSED";
"output.txt";
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
begin --architecture
--Uncomment the line below to test interrupts
interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
clk <= not clk after 50 ns;
reset <= '0' after 500 ns;
pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause <= pause1 or pause2;
gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '1',
use_cache => '1',
log_file => log_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic