Adding PS2, capacitive keyboard examples
This commit is contained in:
carlos
parent
2efe106cf3
commit
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#!/bin/sh
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QT_BASE_DIR="/home/cain/Embedded/ingenic/sakc/build/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.32/qt-everywhere-opensource-src-4.7.0-beta2"
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QT_BASE_DIR="/home/cain/Embedded/ingenic/sakc/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.32/qt-everywhere-opensource-src-4.7.0"
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${QT_BASE_DIR}/bin/qmake -spec ${QT_BASE_DIR}/mkspecs/qws/linux-openwrt-g++ -o Makefile
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make
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[Dolphin]
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Sorting=2
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Timestamp=2010,9,22,22,43,37
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ViewMode=1
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[Dolphin]
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EESchema Schematic File Version 2 date mié 22 sep 2010 13:24:28 COT
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LIBS:/home/ari/Documentos/ps2/Design files/header_20x2,/home/ari/Documentos/ps2/Design files/header_4,/home/ari/Documentos/ps2/Design files/header_2,/home/ari/kicad/SparkFun.lbr/SparkFun,power,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./ps2.cache
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 1 1
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Title "PS2"
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Date "22 sep 2010"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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Wire Wire Line
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EESchema-DOCLIB Version 2.0 mié 22 sep 2010 13:56:54 COT
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#
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$CMP R
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D Resistance
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K R DEV
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$ENDCMP
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#
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#End Doc Library
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EESchema-LIBRARY Version mié 22 sep 2010 13:56:54 COT
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#
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#
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# HEADER_2
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#
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DEF HEADER_2 J 0 40 Y Y 1 F N
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F0 "J" -250 200 60 H V C CNN
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F1 "HEADER_2" 0 0 60 H V C CNN
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DRAW
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ENDDEF
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#
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# HEADER_20X2
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#
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DEF HEADER_20X2 J 0 40 Y Y 1 F N
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F0 "J" -150 1250 60 H V C CNN
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F1 "HEADER_20X2" 0 0 60 H V C CNN
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DRAW
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|
||||
X ~ 29 250 400 150 L 25 25 1 1 B
|
||||
X ~ 27 250 450 150 L 25 25 1 1 B
|
||||
X ~ 25 250 500 150 L 25 25 1 1 B
|
||||
X ~ 23 250 550 150 L 25 25 1 1 B
|
||||
X ~ 21 250 600 150 L 25 25 1 1 B
|
||||
X ~ 19 250 650 150 L 25 25 1 1 B
|
||||
X ~ 17 250 700 150 L 25 25 1 1 B
|
||||
X ~ 15 250 750 150 L 25 25 1 1 B
|
||||
X ~ 13 250 800 150 L 25 25 1 1 B
|
||||
X ~ 11 250 850 150 L 25 25 1 1 B
|
||||
X ~ 9 250 900 150 L 25 25 1 1 B
|
||||
X ~ 7 250 950 150 L 25 25 1 1 B
|
||||
X ~ 5 250 1000 150 L 25 25 1 1 B
|
||||
X ~ 3 250 1050 150 L 25 25 1 1 B
|
||||
X ~ 1 250 1100 150 L 25 25 1 1 B
|
||||
X ~ 40 -350 150 150 R 25 25 1 1 B
|
||||
X ~ 38 -350 200 150 R 25 25 1 1 B
|
||||
X ~ 36 -350 250 150 R 25 25 1 1 B
|
||||
X ~ 34 -350 300 150 R 25 25 1 1 B
|
||||
X ~ 32 -350 350 150 R 25 25 1 1 B
|
||||
X ~ 30 -350 400 150 R 25 25 1 1 B
|
||||
X ~ 28 -350 450 150 R 25 25 1 1 B
|
||||
X ~ 26 -350 500 150 R 25 25 1 1 B
|
||||
X ~ 24 -350 550 150 R 25 25 1 1 B
|
||||
X ~ 22 -350 600 150 R 25 25 1 1 B
|
||||
X ~ 20 -350 650 150 R 25 25 1 1 B
|
||||
X ~ 18 -350 700 150 R 25 25 1 1 B
|
||||
X ~ 16 -350 750 150 R 25 25 1 1 B
|
||||
X ~ 14 -350 800 150 R 25 25 1 1 B
|
||||
X ~ 12 -350 850 150 R 25 25 1 1 B
|
||||
X ~ 10 -350 900 150 R 25 25 1 1 B
|
||||
X ~ 8 -350 950 150 R 25 25 1 1 B
|
||||
X ~ 6 -350 1000 150 R 25 25 1 1 B
|
||||
X ~ 4 -350 1050 150 R 25 25 1 1 B
|
||||
X ~ 2 -350 1100 150 R 25 25 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# HEADER_4
|
||||
#
|
||||
DEF HEADER_4 J 0 40 Y Y 1 F N
|
||||
F0 "J" -200 200 60 H V C CNN
|
||||
F1 "HEADER_4" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 5 0 1 0 50 100 50 50 0 50 0 100 0 100 N
|
||||
S 100 350 -50 100 0 1 0 N
|
||||
P 5 0 1 0 0 350 0 400 50 400 50 350 50 350 N
|
||||
X ~ 4 250 150 150 L 25 25 1 1 B
|
||||
X ~ 3 250 200 150 L 25 25 1 1 B
|
||||
X ~ 2 250 250 150 L 25 25 1 1 B
|
||||
X ~ 1 250 300 150 L 25 25 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# MINI-DIN6PTH
|
||||
#
|
||||
DEF MINI-DIN6PTH ?? 0 40 Y N 1 L N
|
||||
F0 "??" 0 0 60 H V C CNN
|
||||
F1 "MINI-DIN6PTH" 0 0 60 H V C CNN
|
||||
DRAW
|
||||
P 2 1 0 0 50 -300 -200 -300 N
|
||||
P 2 1 0 0 -50 0 0 0 N
|
||||
P 2 1 0 0 -50 -100 0 -100 N
|
||||
P 2 1 0 0 -50 -200 0 -200 N
|
||||
P 2 1 0 0 -200 400 -200 -300 N
|
||||
P 2 1 0 0 50 -300 50 400 N
|
||||
P 2 1 0 0 -200 400 50 400 N
|
||||
P 2 1 0 0 -50 200 0 200 N
|
||||
P 2 1 0 0 -50 100 0 100 N
|
||||
P 2 1 0 0 -50 300 0 300 N
|
||||
X 1 1 200 -200 200 L 40 40 1 1 P
|
||||
X 2 2 200 -100 200 L 40 40 1 1 P
|
||||
X 3 3 200 0 200 L 40 40 1 1 P
|
||||
X 4 4 200 100 200 L 40 40 1 1 P
|
||||
X 5 5 200 200 200 L 40 40 1 1 P
|
||||
X 6 6 200 300 200 L 40 40 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# R
|
||||
#
|
||||
DEF R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "R" 0 0 50 V V C CNN
|
||||
$FPLIST
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 150 40 -150 0 1 8 N
|
||||
X ~ 1 0 250 100 D 60 60 1 1 P
|
||||
X ~ 2 0 -250 100 U 60 60 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#EndLibrary
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
Cmp-Mod V01 Created by CVpcb (20090216-final) date = mié 22 sep 2010 15:03:47 COT
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A3459;
|
||||
Reference = J1;
|
||||
ValeurCmp = HEADER_20X2;
|
||||
IdModule = J19;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A34CA;
|
||||
Reference = J2;
|
||||
ValeurCmp = HEADER_2;
|
||||
IdModule = J18;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A34A5;
|
||||
Reference = J3;
|
||||
ValeurCmp = HEADER_4;
|
||||
IdModule = J7;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A34A9;
|
||||
Reference = J4;
|
||||
ValeurCmp = HEADER_4;
|
||||
IdModule = J7;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A3321;
|
||||
Reference = JS1;
|
||||
ValeurCmp = MINI-DIN6PTH;
|
||||
IdModule = SparkFun-MINI-DIN6;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A33C5;
|
||||
Reference = JS2;
|
||||
ValeurCmp = MINI-DIN6PTH;
|
||||
IdModule = SparkFun-MINI-DIN6;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A308B;
|
||||
Reference = R1;
|
||||
ValeurCmp = 270;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A32C5;
|
||||
Reference = R2;
|
||||
ValeurCmp = 270;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A32D1;
|
||||
Reference = R3;
|
||||
ValeurCmp = 270;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A32D6;
|
||||
Reference = R4;
|
||||
ValeurCmp = 270;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A3558;
|
||||
Reference = R5;
|
||||
ValeurCmp = 10K;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A3588;
|
||||
Reference = R6;
|
||||
ValeurCmp = 10K;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A358F;
|
||||
Reference = R7;
|
||||
ValeurCmp = 10K;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /4C9A359B;
|
||||
Reference = R8;
|
||||
ValeurCmp = 10K;
|
||||
IdModule = R1;
|
||||
EndCmp
|
||||
|
||||
EndListe
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
M48
|
||||
;DRILL file {PCBnew (20090216-final)} date vie 24 sep 2010 19:05:15 COT
|
||||
;FORMAT={2:4/ absolute / inch / suppress leading zeros}
|
||||
R,T
|
||||
VER,1
|
||||
FMAT,2
|
||||
INCH,TZ
|
||||
TCST,OFF
|
||||
ICI,OFF
|
||||
ATC,ON
|
||||
T1C0.034
|
||||
T2C0.035
|
||||
T3C0.042
|
||||
T4C0.087
|
||||
T5C0.118
|
||||
%
|
||||
M47
|
||||
G05
|
||||
M72
|
||||
T1
|
||||
X69250Y36300
|
||||
X69250Y37350
|
||||
X70250Y36300
|
||||
X70250Y37350
|
||||
X71250Y36320
|
||||
X71250Y37370
|
||||
X72250Y36300
|
||||
X72250Y37350
|
||||
X82800Y44850
|
||||
X82800Y45640
|
||||
X82800Y46420
|
||||
X82800Y47210
|
||||
X82800Y48000
|
||||
X82800Y48790
|
||||
X82800Y49570
|
||||
X82800Y50360
|
||||
X82800Y51150
|
||||
X82800Y51940
|
||||
X82800Y52720
|
||||
X82800Y53510
|
||||
X82800Y54300
|
||||
X82800Y55090
|
||||
X82800Y55870
|
||||
X82800Y56660
|
||||
X82800Y57450
|
||||
X82800Y58240
|
||||
X82800Y59020
|
||||
X82800Y59810
|
||||
X83590Y44850
|
||||
X83590Y45640
|
||||
X83590Y46420
|
||||
X83590Y47210
|
||||
X83590Y48000
|
||||
X83590Y48790
|
||||
X83590Y49570
|
||||
X83590Y50360
|
||||
X83590Y51150
|
||||
X83590Y51940
|
||||
X83590Y52720
|
||||
X83590Y53510
|
||||
X83590Y54300
|
||||
X83590Y55090
|
||||
X83590Y55870
|
||||
X83590Y56660
|
||||
X83590Y57450
|
||||
X83590Y58240
|
||||
X83590Y59020
|
||||
X83590Y59810
|
||||
T2
|
||||
X56862Y62470
|
||||
X56862Y63454
|
||||
X57689Y63454
|
||||
X58711Y63454
|
||||
X59538Y62470
|
||||
X59538Y63454
|
||||
X65262Y62570
|
||||
X65262Y63554
|
||||
X66089Y63554
|
||||
X67111Y63554
|
||||
X67938Y62570
|
||||
X67938Y63554
|
||||
T3
|
||||
X73400Y36350
|
||||
X73400Y37350
|
||||
T4
|
||||
X58200Y64950
|
||||
X66600Y65050
|
||||
T5
|
||||
X51190Y37000
|
||||
X51190Y65000
|
||||
X82790Y37000
|
||||
X82790Y65000
|
||||
T0
|
||||
M30
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Control ERC (mié 22 sep 2010 13:03:48 COT)
|
||||
|
||||
***** Hoja / (Root)
|
||||
ERC: Aviso: Pin power_out conectado a Pin BiDi (net 4) (X= 7,400 pulgadas, Y= 1,550 pulgadas
|
||||
ERC: Aviso: Pin power_out conectado a Pin BiDi (net 1) (X= 6,400 pulgadas, Y= 3,150 pulgadas
|
||||
|
||||
>> Errores ERC: 2
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
EESchema (20090216-final) >> Creation date: mié 22 sep 2010 14:39:34 COT
|
||||
|
||||
#Componentes ( orden = Referencia )
|
||||
| J1 HEADER_20X2
|
||||
| J2 HEADER_2
|
||||
| J3 HEADER_4
|
||||
| J4 HEADER_4
|
||||
| JS1 MINI-DIN6PTH
|
||||
| JS2 MINI-DIN6PTH
|
||||
| R1 270
|
||||
| R2 270
|
||||
| R3 270
|
||||
| R4 270
|
||||
| R5 10K
|
||||
| R6 10K
|
||||
| R7 10K
|
||||
| R8 10K
|
||||
#Fin Componentes
|
||||
|
||||
#Componentes ( orden = Valor )
|
||||
| 10K R5
|
||||
| 10K R6
|
||||
| 10K R7
|
||||
| 10K R8
|
||||
| 270 R1
|
||||
| 270 R2
|
||||
| 270 R3
|
||||
| 270 R4
|
||||
| HEADER_2 J2
|
||||
| HEADER_20X2 J1
|
||||
| HEADER_4 J3
|
||||
| HEADER_4 J4
|
||||
| MINI-DIN6PTH JS1
|
||||
| MINI-DIN6PTH JS2
|
||||
#Fin Componentes
|
||||
|
||||
#Fin de Lista
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
# EESchema Netlist Version 1.1 created mié 22 sep 2010 15:03:47 COT
|
||||
(
|
||||
( /4C9A3459 J19 J1 HEADER_20X2
|
||||
( 1 /GND )
|
||||
( 2 ? )
|
||||
( 3 /PS2_DATA1 )
|
||||
( 4 ? )
|
||||
( 5 /PS2_CLK1 )
|
||||
( 6 ? )
|
||||
( 7 /PS2_DATA2 )
|
||||
( 8 ? )
|
||||
( 9 /PS2_CLK2 )
|
||||
( 10 ? )
|
||||
( 11 ? )
|
||||
( 12 ? )
|
||||
( 13 ? )
|
||||
( 14 ? )
|
||||
( 15 ? )
|
||||
( 16 ? )
|
||||
( 17 ? )
|
||||
( 18 ? )
|
||||
( 19 ? )
|
||||
( 20 ? )
|
||||
( 21 ? )
|
||||
( 22 ? )
|
||||
( 23 ? )
|
||||
( 24 ? )
|
||||
( 25 ? )
|
||||
( 26 ? )
|
||||
( 27 ? )
|
||||
( 28 ? )
|
||||
( 29 ? )
|
||||
( 30 ? )
|
||||
( 31 ? )
|
||||
( 32 ? )
|
||||
( 33 ? )
|
||||
( 34 ? )
|
||||
( 35 ? )
|
||||
( 36 ? )
|
||||
( 37 ? )
|
||||
( 38 ? )
|
||||
( 39 ? )
|
||||
( 40 ? )
|
||||
)
|
||||
( /4C9A34CA J18 J2 HEADER_2
|
||||
( 1 ? )
|
||||
( 2 /VCC )
|
||||
)
|
||||
( /4C9A34A5 J7 J3 HEADER_4
|
||||
( 1 ? )
|
||||
( 2 ? )
|
||||
( 3 ? )
|
||||
( 4 ? )
|
||||
)
|
||||
( /4C9A34A9 J7 J4 HEADER_4
|
||||
( 1 ? )
|
||||
( 2 ? )
|
||||
( 3 ? )
|
||||
( 4 ? )
|
||||
)
|
||||
( /4C9A3321 SparkFun-MINI-DIN6 JS1 MINI-DIN6PTH
|
||||
( 1 N-000006 )
|
||||
( 2 ? )
|
||||
( 3 /GND )
|
||||
( 4 /VCC )
|
||||
( 5 N-000005 )
|
||||
( 6 ? )
|
||||
)
|
||||
( /4C9A33C5 SparkFun-MINI-DIN6 JS2 MINI-DIN6PTH
|
||||
( 1 N-000007 )
|
||||
( 2 ? )
|
||||
( 3 /GND )
|
||||
( 4 /VCC )
|
||||
( 5 N-000004 )
|
||||
( 6 ? )
|
||||
)
|
||||
( /4C9A308B R1 R1 270
|
||||
( 1 N-000006 )
|
||||
( 2 /PS2_DATA1 )
|
||||
)
|
||||
( /4C9A32C5 R1 R2 270
|
||||
( 1 N-000005 )
|
||||
( 2 /PS2_CLK1 )
|
||||
)
|
||||
( /4C9A32D1 R1 R3 270
|
||||
( 1 N-000007 )
|
||||
( 2 /PS2_DATA2 )
|
||||
)
|
||||
( /4C9A32D6 R1 R4 270
|
||||
( 1 N-000004 )
|
||||
( 2 /PS2_CLK2 )
|
||||
)
|
||||
( /4C9A3558 R1 R5 10K
|
||||
( 1 N-000006 )
|
||||
( 2 /VCC )
|
||||
)
|
||||
( /4C9A3588 R1 R6 10K
|
||||
( 1 N-000005 )
|
||||
( 2 /VCC )
|
||||
)
|
||||
( /4C9A358F R1 R7 10K
|
||||
( 1 N-000007 )
|
||||
( 2 /VCC )
|
||||
)
|
||||
( /4C9A359B R1 R8 10K
|
||||
( 1 N-000004 )
|
||||
( 2 /VCC )
|
||||
)
|
||||
)
|
||||
*
|
||||
{ Allowed footprints by component:
|
||||
$component R1
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R2
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R3
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R4
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R5
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R6
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R7
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$component R8
|
||||
R?
|
||||
SM0603
|
||||
SM0805
|
||||
$endlist
|
||||
$endfootprintlist
|
||||
}
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
update=mié 22 sep 2010 16:09:33 COT
|
||||
last_client=pcbnew
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
NetFmt=1
|
||||
HPGLSpd=20
|
||||
HPGLDm=15
|
||||
HPGLNum=1
|
||||
offX_A4=0
|
||||
offY_A4=0
|
||||
offX_A3=0
|
||||
offY_A3=0
|
||||
offX_A2=0
|
||||
offY_A2=0
|
||||
offX_A1=0
|
||||
offY_A1=0
|
||||
offX_A0=0
|
||||
offY_A0=0
|
||||
offX_A=0
|
||||
offY_A=0
|
||||
offX_B=0
|
||||
offY_B=0
|
||||
offX_C=0
|
||||
offY_C=0
|
||||
offX_D=0
|
||||
offY_D=0
|
||||
offX_E=0
|
||||
offY_E=0
|
||||
RptD_X=0
|
||||
RptD_Y=100
|
||||
RptLab=1
|
||||
SimCmd=
|
||||
UseNetN=0
|
||||
LabSize=60
|
||||
[eeschema/libraries]
|
||||
LibName1=/home/ari/Documentos/ps2/Design files/header_20x2
|
||||
LibName2=/home/ari/Documentos/ps2/Design files/header_4
|
||||
LibName3=/home/ari/Documentos/ps2/Design files/header_2
|
||||
LibName4=/home/ari/kicad/SparkFun.lbr/SparkFun
|
||||
LibName5=power
|
||||
LibName6=device
|
||||
LibName7=transistors
|
||||
LibName8=conn
|
||||
LibName9=linear
|
||||
LibName10=regul
|
||||
LibName11=74xx
|
||||
LibName12=cmos4000
|
||||
LibName13=adc-dac
|
||||
LibName14=memory
|
||||
LibName15=xilinx
|
||||
LibName16=special
|
||||
LibName17=microcontrollers
|
||||
LibName18=dsp
|
||||
LibName19=microchip
|
||||
LibName20=analog_switches
|
||||
LibName21=motorola
|
||||
LibName22=texas
|
||||
LibName23=intel
|
||||
LibName24=audio
|
||||
LibName25=interface
|
||||
LibName26=digital-audio
|
||||
LibName27=philips
|
||||
LibName28=display
|
||||
LibName29=cypress
|
||||
LibName30=siliconi
|
||||
LibName31=opto
|
||||
LibName32=atmel
|
||||
LibName33=contrib
|
||||
LibName34=valves
|
||||
[common]
|
||||
NetDir=
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=.net
|
||||
[cvpcb/libraries]
|
||||
EquName1=devcms
|
||||
[pcbnew]
|
||||
version=1
|
||||
PadDrlX=320
|
||||
PadDimH=600
|
||||
PadDimV=600
|
||||
ViaDiam=450
|
||||
ViaDril=250
|
||||
ViaAltD=250
|
||||
MViaDia=200
|
||||
MViaDrl=80
|
||||
Isol=60
|
||||
Countlayer=2
|
||||
Lpiste=197
|
||||
RouteTo=15
|
||||
RouteBo=0
|
||||
TypeVia=3
|
||||
Segm45=1
|
||||
Racc45=1
|
||||
SgPcb45=1
|
||||
TxtPcbV=800
|
||||
TxtPcbH=600
|
||||
TxtModV=600
|
||||
TxtModH=600
|
||||
TxtModW=79
|
||||
HPGLnum=1
|
||||
HPGdiam=15
|
||||
HPGLSpd=20
|
||||
HPGLrec=2
|
||||
HPGLorg=0
|
||||
VEgarde=100
|
||||
DrawLar=79
|
||||
EdgeLar=79
|
||||
TxtLar=120
|
||||
MSegLar=79
|
||||
WpenSer=10
|
||||
[pcbnew/libraries]
|
||||
LibDir=
|
||||
LibName1=/home/ari/Documentos/ps2/N_MODELS/J18
|
||||
LibName2=/home/ari/Documentos/ps2/N_MODELS/J13
|
||||
LibName3=sockets
|
||||
LibName4=/home/ari/Documentos/ps2/N_MODELS/R1
|
||||
LibName5=/home/ari/Documentos/ps2/N_MODELS/J7
|
||||
LibName6=/home/ari/Documentos/ps2/N_MODELS/J19
|
||||
LibName7=/home/ari/kicad/SparkFun.lbr/SparkFun
|
||||
LibName8=connect
|
||||
LibName9=discret
|
||||
LibName10=pin_array
|
||||
LibName11=divers
|
||||
LibName12=libcms
|
||||
LibName13=display
|
||||
LibName14=valves
|
||||
LibName15=led
|
||||
LibName16=dip_sockets
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
EESchema Schematic File Version 2 date mié 22 sep 2010 13:56:54 COT
|
||||
LIBS:/home/ari/Documentos/ps2/Design files/header_20x2,/home/ari/Documentos/ps2/Design files/header_4,/home/ari/Documentos/ps2/Design files/header_2,/home/ari/kicad/SparkFun.lbr/SparkFun,power,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./ps2.cache
|
||||
EELAYER 24 0
|
||||
EELAYER END
|
||||
$Descr A4 11700 8267
|
||||
Sheet 1 1
|
||||
Title "PS2"
|
||||
Date "22 sep 2010"
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
7450 1550 7300 1550
|
||||
Wire Wire Line
|
||||
5450 2300 5450 2500
|
||||
Wire Wire Line
|
||||
5550 2300 5550 2500
|
||||
Wire Wire Line
|
||||
4900 3200 4900 3400
|
||||
Wire Wire Line
|
||||
5850 3200 5850 3400
|
||||
Wire Wire Line
|
||||
4700 3800 4700 3200
|
||||
Wire Wire Line
|
||||
5250 3900 5250 3200
|
||||
Wire Wire Line
|
||||
7800 1700 7300 1700
|
||||
Wire Wire Line
|
||||
7800 1600 7300 1600
|
||||
Wire Wire Line
|
||||
5850 2700 5650 2700
|
||||
Wire Wire Line
|
||||
5650 2700 5650 2300
|
||||
Wire Wire Line
|
||||
4900 2700 4700 2700
|
||||
Wire Wire Line
|
||||
4300 2300 4300 2700
|
||||
Wire Wire Line
|
||||
4700 2700 4700 2300
|
||||
Wire Wire Line
|
||||
4300 2700 4500 2700
|
||||
Wire Wire Line
|
||||
5250 2300 5250 2700
|
||||
Wire Wire Line
|
||||
5250 2700 5450 2700
|
||||
Wire Wire Line
|
||||
7800 1650 7300 1650
|
||||
Wire Wire Line
|
||||
7800 1750 7300 1750
|
||||
Wire Wire Line
|
||||
5650 3850 5650 3200
|
||||
Wire Wire Line
|
||||
4300 3850 4300 3200
|
||||
Wire Wire Line
|
||||
6500 3150 6300 3150
|
||||
Wire Wire Line
|
||||
5450 3200 5450 3400
|
||||
Wire Wire Line
|
||||
4500 3200 4500 3400
|
||||
Wire Wire Line
|
||||
4600 2300 4600 2500
|
||||
Wire Wire Line
|
||||
4500 2300 4500 2500
|
||||
Text Label 7450 1550 0 39 ~ 0
|
||||
GND
|
||||
Text Label 4500 2500 1 39 ~ 0
|
||||
GND
|
||||
Text Label 5450 2500 1 39 ~ 0
|
||||
GND
|
||||
Text Label 4600 2500 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 5550 2500 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 4500 3400 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 4900 3400 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 5450 3400 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 5850 3400 1 39 ~ 0
|
||||
VCC
|
||||
Text Label 6300 3150 0 39 ~ 0
|
||||
VCC
|
||||
Text Label 7800 1750 0 39 ~ 0
|
||||
PS2_CLK2
|
||||
Text Label 7800 1700 0 39 ~ 0
|
||||
PS2_DATA2
|
||||
Text Label 7800 1650 0 39 ~ 0
|
||||
PS2_CLK1
|
||||
Text Label 7800 1600 0 39 ~ 0
|
||||
PS2_DATA1
|
||||
Text Label 5650 3850 1 39 ~ 0
|
||||
PS2_CLK2
|
||||
Text Label 5250 3900 1 39 ~ 0
|
||||
PS2_DATA2
|
||||
Text Label 4700 3800 1 39 ~ 0
|
||||
PS2_CLK1
|
||||
Text Label 4300 3850 1 39 ~ 0
|
||||
PS2_DATA1
|
||||
NoConn ~ 7300 1800
|
||||
NoConn ~ 7300 1850
|
||||
NoConn ~ 7300 1900
|
||||
NoConn ~ 7300 1950
|
||||
NoConn ~ 7300 2000
|
||||
NoConn ~ 7300 2050
|
||||
NoConn ~ 7300 2100
|
||||
NoConn ~ 7300 2150
|
||||
NoConn ~ 7300 2200
|
||||
NoConn ~ 7300 2250
|
||||
NoConn ~ 7300 2300
|
||||
NoConn ~ 7300 2350
|
||||
NoConn ~ 7300 2400
|
||||
NoConn ~ 7300 2450
|
||||
NoConn ~ 7300 2500
|
||||
NoConn ~ 6700 2500
|
||||
NoConn ~ 6700 2450
|
||||
NoConn ~ 6700 2400
|
||||
NoConn ~ 6700 2350
|
||||
NoConn ~ 6700 2300
|
||||
NoConn ~ 6700 2250
|
||||
NoConn ~ 6700 2200
|
||||
NoConn ~ 6700 2150
|
||||
NoConn ~ 6700 2100
|
||||
NoConn ~ 6700 2050
|
||||
NoConn ~ 6700 2000
|
||||
NoConn ~ 6700 1950
|
||||
NoConn ~ 6700 1900
|
||||
NoConn ~ 6700 1850
|
||||
NoConn ~ 6700 1800
|
||||
NoConn ~ 6700 1750
|
||||
NoConn ~ 6700 1700
|
||||
NoConn ~ 6700 1650
|
||||
NoConn ~ 6700 1600
|
||||
NoConn ~ 6700 1550
|
||||
NoConn ~ 8150 2550
|
||||
NoConn ~ 8150 2500
|
||||
NoConn ~ 8150 2450
|
||||
NoConn ~ 8150 2400
|
||||
NoConn ~ 8150 2150
|
||||
NoConn ~ 8150 2100
|
||||
NoConn ~ 8150 2050
|
||||
NoConn ~ 8150 2000
|
||||
NoConn ~ 6500 3250
|
||||
NoConn ~ 5750 2300
|
||||
NoConn ~ 5350 2300
|
||||
NoConn ~ 4800 2300
|
||||
NoConn ~ 4400 2300
|
||||
$Comp
|
||||
L R R8
|
||||
U 1 1 4C9A359B
|
||||
P 5850 2950
|
||||
F 0 "R8" V 5930 2950 50 0000 C CNN
|
||||
F 1 "10K" V 5850 2950 50 0000 C CNN
|
||||
1 5850 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R7
|
||||
U 1 1 4C9A358F
|
||||
P 5450 2950
|
||||
F 0 "R7" V 5530 2950 50 0000 C CNN
|
||||
F 1 "10K" V 5450 2950 50 0000 C CNN
|
||||
1 5450 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R6
|
||||
U 1 1 4C9A3588
|
||||
P 4900 2950
|
||||
F 0 "R6" V 4980 2950 50 0000 C CNN
|
||||
F 1 "10K" V 4900 2950 50 0000 C CNN
|
||||
1 4900 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R5
|
||||
U 1 1 4C9A3558
|
||||
P 4500 2950
|
||||
F 0 "R5" V 4580 2950 50 0000 C CNN
|
||||
F 1 "10K" V 4500 2950 50 0000 C CNN
|
||||
1 4500 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L HEADER_2 J2
|
||||
U 1 1 4C9A34CA
|
||||
P 6800 3000
|
||||
F 0 "J2" H 6550 3200 60 0000 C CNN
|
||||
F 1 "HEADER_2" H 6800 3000 60 0000 C CNN
|
||||
1 6800 3000
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L HEADER_4 J4
|
||||
U 1 1 4C9A34A9
|
||||
P 7900 2700
|
||||
F 0 "J4" H 7700 2900 60 0000 C CNN
|
||||
F 1 "HEADER_4" H 7900 2700 60 0000 C CNN
|
||||
1 7900 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L HEADER_4 J3
|
||||
U 1 1 4C9A34A5
|
||||
P 7900 2300
|
||||
F 0 "J3" H 7700 2500 60 0000 C CNN
|
||||
F 1 "HEADER_4" H 7900 2300 60 0000 C CNN
|
||||
1 7900 2300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L HEADER_20X2 J1
|
||||
U 1 1 4C9A3459
|
||||
P 7050 2650
|
||||
F 0 "J1" H 6900 3900 60 0000 C CNN
|
||||
F 1 "HEADER_20X2" H 7050 2650 60 0000 C CNN
|
||||
1 7050 2650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L MINI-DIN6PTH ?
|
||||
U 1 1 4C9A33C5
|
||||
P 5450 2100
|
||||
AR Path="/4C9A3321" Ref="?" Part="1"
|
||||
AR Path="/4C9A33C5" Ref="JS2" Part="1"
|
||||
F 0 "JS2" V 5150 2100 60 0000 C CNN
|
||||
F 1 "MINI-DIN6PTH" V 5300 2150 60 0000 C CNN
|
||||
1 5450 2100
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L MINI-DIN6PTH JS1
|
||||
U 1 1 4C9A3321
|
||||
P 4500 2100
|
||||
F 0 "JS1" V 4200 2100 60 0000 C CNN
|
||||
F 1 "MINI-DIN6PTH" V 4350 2150 60 0000 C CNN
|
||||
1 4500 2100
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R4
|
||||
U 1 1 4C9A32D6
|
||||
P 5650 2950
|
||||
F 0 "R4" V 5730 2950 50 0000 C CNN
|
||||
F 1 "270" V 5650 2950 50 0000 C CNN
|
||||
1 5650 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R3
|
||||
U 1 1 4C9A32D1
|
||||
P 5250 2950
|
||||
F 0 "R3" V 5330 2950 50 0000 C CNN
|
||||
F 1 "270" V 5250 2950 50 0000 C CNN
|
||||
1 5250 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R2
|
||||
U 1 1 4C9A32C5
|
||||
P 4700 2950
|
||||
F 0 "R2" V 4780 2950 50 0000 C CNN
|
||||
F 1 "270" V 4700 2950 50 0000 C CNN
|
||||
1 4700 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L R R1
|
||||
U 1 1 4C9A308B
|
||||
P 4300 2950
|
||||
F 0 "R1" V 4380 2950 50 0000 C CNN
|
||||
F 1 "270" V 4300 2950 50 0000 C CNN
|
||||
1 4300 2950
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# Initial commands
|
||||
|
||||
# Routing commands
|
||||
bestsave on C:\Documents and Settings\BlueDeep\Mis documentos\Orcad\Conector_PS2\Nueva carpeta\PS2-7.WRE
|
||||
status_file C:\Documents and Settings\BlueDeep\Mis documentos\Orcad\Conector_PS2\Nueva carpeta\PS2-7.STS
|
||||
bus diagonal
|
||||
smart_route
|
||||
|
||||
# DFM commands
|
||||
|
||||
# Final commands
|
||||
write routes C:\Documents and Settings\BlueDeep\Mis documentos\Orcad\Conector_PS2\Nueva carpeta\PS2-7.RTE
|
||||
Binary file not shown.
|
|
@ -0,0 +1,571 @@
|
|||
(PCB
|
||||
'C:\Documents and Settings\BlueDeep\Mis documentos\Orcad\Conector_PS2\Nueva carpeta\PS2-7.MAX'
|
||||
(parser
|
||||
(space_in_quoted_tokens on)
|
||||
(string_quote ')
|
||||
(host_cad 'OrCAD Layout')
|
||||
(host_version 9.1)
|
||||
)
|
||||
(resolution mm 100000)
|
||||
(structure
|
||||
(boundary(rect pcb -161.98850 2.15900 -61.84900 92.64650)
|
||||
)
|
||||
(boundary(path signal 0.20000 -152.14600 83.56600 -61.97600 83.56600
|
||||
-61.97600 2.54000 -152.14600 2.54000 -152.14600 83.56600)
|
||||
)
|
||||
(via VIA1
|
||||
)
|
||||
(control
|
||||
(off_grid OFF)
|
||||
(force_to_terminal_point ON)
|
||||
)
|
||||
(grid via 0.00000)
|
||||
(grid wire 1.50000)
|
||||
(grid place 0.20000)
|
||||
(rule(clearance 0.25400))
|
||||
(rule(width 0.25400))
|
||||
(layer TOP(type signal)(direction horizontal)
|
||||
)
|
||||
(layer GND(type power)
|
||||
)
|
||||
(layer POWER(type power)
|
||||
)
|
||||
(layer BOTTOM(type signal)(direction vertical)
|
||||
)
|
||||
)
|
||||
(placement
|
||||
(component MOLEX_87333_20X2
|
||||
(place J1 -67.80000 58.40000 front 270.00 (PN HEADER_20X2)(property(value
|
||||
'HEADER 20X2')))
|
||||
)
|
||||
(component POLCON.100/VH/TM1SQS/W.300/2_3
|
||||
(place J2 -92.40000 80.60000 front 270.00 (PN HEADER_2)(property(value
|
||||
'HEADER 2')))
|
||||
)
|
||||
(component SIP/TM/L.400/4
|
||||
(place J3 -95.40000 77.40000 front 180.00 (PN HEADER_4)(property(value
|
||||
'HEADER 4')))
|
||||
)
|
||||
(component SIP/TM/L.400/4
|
||||
(place J4 -95.50000 80.40000 front 180.00 (PN HEADER_4)(property(value
|
||||
'HEADER 4')))
|
||||
)
|
||||
(component DINC/MIN_TM/6
|
||||
(place JS1 -132.00000 2.80000 front 180.00 (PN 'M-DIN_6-R'))
|
||||
)
|
||||
(component DINC/MIN_TM/6
|
||||
(place JS2 -111.60000 2.80000 front 180.00 (PN 'M-DIN_6-R'))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R1 -129.80000 56.40000 front 180.00 (PN R)(property(value 270)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R2 -127.80000 54.40000 front 180.00 (PN R)(property(value 270)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R3 -111.60000 52.40000 front 180.00 (PN R)(property(value 270)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R4 -109.40000 50.40000 front 180.00 (PN R)(property(value 270)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R5 -138.40000 22.40000 front 90.00 (PN R)(property(value 10k)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R6 -121.80000 13.80000 front 0.00 (PN R)(property(value 10k)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R7 -120.00000 20.60000 front 180.00 (PN R)(property(value 10k)))
|
||||
)
|
||||
(component SM_R_0603
|
||||
(place R8 -107.00000 22.40000 front 90.00 (PN R)(property(value 10k)))
|
||||
)
|
||||
(component SIP/TM/L.100/1
|
||||
(place 15 -147.00000 78.60000 front 0.00 )
|
||||
)
|
||||
(component SIP/TM/L.100/1
|
||||
(place 16 -66.40000 78.60000 front 0.00 )
|
||||
)
|
||||
(component SIP/TM/L.100/1
|
||||
(place 17 -66.60000 7.40000 front 0.00 )
|
||||
)
|
||||
(component SIP/TM/L.100/1
|
||||
(place 18 -147.40000 7.20000 front 0.00 )
|
||||
)
|
||||
)
|
||||
(library
|
||||
(image VIA1
|
||||
(pin VIA1 FV 0.00000 0.00000)
|
||||
)
|
||||
(image VIA2
|
||||
)
|
||||
(image VIA3
|
||||
)
|
||||
(image VIA4
|
||||
)
|
||||
(image VIA5
|
||||
)
|
||||
(image VIA6
|
||||
)
|
||||
(image VIA7
|
||||
)
|
||||
(image VIA8
|
||||
)
|
||||
(image VIA9
|
||||
)
|
||||
(image VIA10
|
||||
)
|
||||
(image VIA11
|
||||
)
|
||||
(image VIA12
|
||||
)
|
||||
(image VIA13
|
||||
)
|
||||
(image VIA14
|
||||
)
|
||||
(image VIA15
|
||||
)
|
||||
(image VIA16
|
||||
)
|
||||
(image BLKCON.156/VH/TM1SQS/W.156/2
|
||||
(outline(path TOP 0.02539 -2.28091 -2.08279 6.24331 -2.08279
|
||||
6.24331 2.08279 -2.28091 2.08279 -2.28091 -2.08279)
|
||||
)
|
||||
(pin BCON156T.llb_pad1 1 0.00000 0.00000)
|
||||
(pin BCON156T.llb_pad2 2 3.96239 0.00000)
|
||||
)
|
||||
(image DINC/MIN_TM/6
|
||||
(outline(path TOP 13.00479 -8.50899 -13.20799 8.38200 -13.20799
|
||||
8.38200 0.25400 -8.50899 0.25400 -8.50899 -13.20799)
|
||||
)
|
||||
(pin TM_035H_055P_SQ 1 -1.29539 -8.50899)
|
||||
(pin TM_035H_055P_RND 2 1.29539 -8.50899)
|
||||
(pin TM_035H_055P_RND 3 -3.35279 -8.50899)
|
||||
(pin TM_035H_055P_RND 4 3.35279 -8.50899)
|
||||
(pin TM_035H_055P_RND 5 -3.35279 -10.99819)
|
||||
(pin TM_035H_055P_RND 6 3.35279 -10.99819)
|
||||
(pin TM_091H_112P_RND M1 -6.75639 -5.51179)
|
||||
(pin TM_091H_112P_RND M2 0.00000 -4.69899)
|
||||
(pin TM_091H_112P_RND M3 6.75639 -5.51179)
|
||||
)
|
||||
(image SM_R_0603
|
||||
(outline(path TOP 0.55879 -1.52399 -0.76199 -1.52399 0.76200
|
||||
1.52400 0.76200 1.52400 -0.76199 -1.52399 -0.76199)
|
||||
)
|
||||
(pin RT30X35SM(rotate 90.00) 1 -0.82549 0.00000)
|
||||
(pin RT30X35SM(rotate 90.00) 2 0.82549 0.00000)
|
||||
)
|
||||
(image MOLEX_87333_20X2
|
||||
(pin RD55D34 1 0.00000 0.00000)
|
||||
(pin RD55D34 2 0.00000 2.00659)
|
||||
(pin RD55D34 3 2.00659 0.00000)
|
||||
(pin RD55D34 4 2.00659 2.00659)
|
||||
(pin RD55D34 5 3.98779 0.00000)
|
||||
(pin RD55D34 6 3.98779 2.00659)
|
||||
(pin RD55D34 7 5.99439 0.00000)
|
||||
(pin RD55D34 8 5.99439 2.00659)
|
||||
(pin RD55D34 9 8.00100 0.00000)
|
||||
(pin RD55D34 10 8.00100 2.00659)
|
||||
(pin RD55D34 11 10.00759 0.00000)
|
||||
(pin RD55D34 12 10.00759 2.00659)
|
||||
(pin RD55D34 13 11.98879 0.00000)
|
||||
(pin RD55D34 14 11.98879 2.00659)
|
||||
(pin RD55D34 15 13.99539 0.00000)
|
||||
(pin RD55D34 16 13.99539 2.00659)
|
||||
(pin RD55D34 17 16.00200 0.00000)
|
||||
(pin RD55D34 18 16.00200 2.00659)
|
||||
(pin RD55D34 19 18.00859 0.00000)
|
||||
(pin RD55D34 20 18.00859 2.00659)
|
||||
(pin RD55D34 21 19.98979 0.00000)
|
||||
(pin RD55D34 22 19.98979 2.00659)
|
||||
(pin RD55D34 23 21.99639 0.00000)
|
||||
(pin RD55D34 24 21.99639 2.00659)
|
||||
(pin RD55D34 25 24.00300 0.00000)
|
||||
(pin RD55D34 26 24.00300 2.00659)
|
||||
(pin RD55D34 27 26.00959 0.00000)
|
||||
(pin RD55D34 28 26.00959 2.00659)
|
||||
(pin RD55D34 29 27.99079 0.00000)
|
||||
(pin RD55D34 30 27.99079 2.00659)
|
||||
(pin RD55D34 31 29.99739 0.00000)
|
||||
(pin RD55D34 32 29.99739 2.00659)
|
||||
(pin RD55D34 33 32.00400 0.00000)
|
||||
(pin RD55D34 34 32.00400 2.00659)
|
||||
(pin RD55D34 35 34.01059 0.00000)
|
||||
(pin RD55D34 36 34.01059 2.00659)
|
||||
(pin RD55D34 37 35.99179 0.00000)
|
||||
(pin RD55D34 38 35.99179 2.00659)
|
||||
(pin RD55D34 39 37.99839 0.00000)
|
||||
(pin RD55D34 40 37.99839 2.00659)
|
||||
)
|
||||
(image POLCON.100/VH/TM1SQS/W.300/2
|
||||
(outline(path TOP 0.02539 -1.84657 -4.07161 4.22909 -4.07161
|
||||
4.22909 3.91159 -1.84657 3.91159 -1.84657 -4.07161)
|
||||
)
|
||||
(pin PCON100T.llb_pad1 1 0.00000 0.00000)
|
||||
(pin PCON100T.llb_pad2 2 2.54000 0.00000)
|
||||
)
|
||||
(image SIP/TM/L.100/1
|
||||
(pin SIP.llb_pad2_1 1 -0.00507 0.00000)
|
||||
)
|
||||
(image SIP/TM/L.400/4
|
||||
(outline(path TOP 0.02539 -1.62559 -1.49859 8.86459 -1.49859
|
||||
8.86459 1.37159 -1.62559 1.37159 -1.62559 -1.49859)
|
||||
)
|
||||
(pin SIP.llb_pad1 1 0.00000 0.00000)
|
||||
(pin SIP.llb_pad2 2 2.54000 0.00000)
|
||||
(pin SIP.llb_pad2 3 5.08000 0.00000)
|
||||
(pin SIP.llb_pad2 4 7.62000 0.00000)
|
||||
)
|
||||
(image POLCON.100/VH/TM1SQS/W.300/2_3
|
||||
(pin PCON100T.llb_pad1 1 0.00000 0.00000)
|
||||
(pin PCON100T.llb_pad2 2 2.54000 0.00000)
|
||||
)
|
||||
(padstack VIA1
|
||||
(shape(circle TOP 0.76200))
|
||||
(shape(circle BOTTOM 0.76200))
|
||||
(shape(circle GND 1.52400))
|
||||
(shape(circle POWER 1.52400))
|
||||
)
|
||||
(padstack T1
|
||||
(shape(circle TOP 1.52400))
|
||||
(shape(circle BOTTOM 1.52400))
|
||||
(shape(circle GND 2.03200))
|
||||
(shape(circle POWER 2.03200))
|
||||
)
|
||||
(padstack T2
|
||||
(shape(rect TOP -0.76200 -0.76200 0.76200 0.76200))
|
||||
(shape(rect BOTTOM -0.76200 -0.76200 0.76200 0.76200))
|
||||
(shape(circle GND 2.03200))
|
||||
(shape(circle POWER 2.03200))
|
||||
)
|
||||
(padstack T7
|
||||
(shape(circle TOP 0.76200))
|
||||
(shape(circle BOTTOM 0.76200))
|
||||
(shape(circle GND 1.52400))
|
||||
(shape(circle POWER 1.52400))
|
||||
)
|
||||
(padstack BCON156T.llb_pad1
|
||||
(shape(rect TOP -1.27000 -1.27000 1.27000 1.27000))
|
||||
(shape(rect BOTTOM -1.27000 -1.27000 1.27000 1.27000))
|
||||
(shape(rect GND -1.52400 -1.52400 1.52400 1.52400))
|
||||
(shape(rect POWER -1.52400 -1.52400 1.52400 1.52400))
|
||||
)
|
||||
(padstack BCON156T.llb_pad2
|
||||
(shape(circle TOP 2.54000))
|
||||
(shape(circle BOTTOM 2.54000))
|
||||
(shape(circle GND 3.04800))
|
||||
(shape(circle POWER 3.04800))
|
||||
)
|
||||
(padstack TM_035H_055P_SQ
|
||||
(shape(rect TOP -0.69849 -0.69849 0.69849 0.69849))
|
||||
(shape(rect BOTTOM -0.69849 -0.69849 0.69849 0.69849))
|
||||
(shape(rect GND -0.95249 -0.95249 0.95249 0.95249))
|
||||
(shape(rect POWER -0.95249 -0.95249 0.95249 0.95249))
|
||||
)
|
||||
(padstack TM_035H_055P_RND
|
||||
(shape(circle TOP 1.39698))
|
||||
(shape(circle BOTTOM 1.39698))
|
||||
(shape(circle GND 1.90498))
|
||||
(shape(circle POWER 1.90498))
|
||||
)
|
||||
(padstack TM_091H_112P_RND
|
||||
(shape(circle TOP 2.84478))
|
||||
(shape(circle BOTTOM 2.84478))
|
||||
(shape(circle GND 3.35278))
|
||||
(shape(circle POWER 3.35278))
|
||||
)
|
||||
(padstack RT30X35SM
|
||||
(shape(rect TOP -0.38100 -0.44449 0.38100 0.44449))
|
||||
)
|
||||
(padstack RD55D34
|
||||
(shape(circle TOP 1.34958))
|
||||
(shape(circle BOTTOM 1.34958))
|
||||
(shape(circle GND 1.62558))
|
||||
(shape(circle POWER 1.62558))
|
||||
)
|
||||
(padstack PCON100T.llb_pad1
|
||||
(shape(rect TOP -0.78739 -0.78739 0.78739 0.78739))
|
||||
(shape(rect BOTTOM -0.78739 -0.78739 0.78739 0.78739))
|
||||
(shape(rect GND -1.04139 -1.04139 1.04139 1.04139))
|
||||
(shape(rect POWER -1.04139 -1.04139 1.04139 1.04139))
|
||||
)
|
||||
(padstack PCON100T.llb_pad2
|
||||
(shape(circle TOP 1.57478))
|
||||
(shape(circle BOTTOM 1.57478))
|
||||
(shape(circle GND 2.08278))
|
||||
(shape(circle POWER 2.08278))
|
||||
)
|
||||
(padstack SIP.llb_pad2_1
|
||||
(shape(circle TOP 8.00014))
|
||||
(shape(circle BOTTOM 8.00014))
|
||||
(shape(circle GND 2.99972))
|
||||
(shape(circle POWER 2.99972))
|
||||
)
|
||||
(padstack SIP.llb_pad1
|
||||
(shape(rect TOP -0.69849 -0.69849 0.69849 0.69849))
|
||||
(shape(rect BOTTOM -0.69849 -0.69849 0.69849 0.69849))
|
||||
(shape(rect GND -0.95249 -0.95249 0.95249 0.95249))
|
||||
(shape(rect POWER -0.95249 -0.95249 0.95249 0.95249))
|
||||
)
|
||||
(padstack SIP.llb_pad2
|
||||
(shape(circle TOP 1.39698))
|
||||
(shape(circle BOTTOM 1.39698))
|
||||
(shape(circle GND 1.90498))
|
||||
(shape(circle POWER 1.90498))
|
||||
)
|
||||
)
|
||||
(part_library
|
||||
(logical_part HEADER_2
|
||||
(pin 1 0 none 1 1 0)
|
||||
(pin 2 0 none 1 2 0)
|
||||
)
|
||||
(logical_part 'M-DIN_6-R'
|
||||
(pin 1 0 none 1 1 0)
|
||||
(pin 2 0 none 1 2 0)
|
||||
(pin 3 0 none 1 3 0)
|
||||
(pin 4 0 none 1 4 0)
|
||||
(pin 5 0 none 1 5 0)
|
||||
(pin 6 0 none 1 6 0)
|
||||
(pin M1 0 none 0 7 0)
|
||||
(pin M2 0 none 0 8 0)
|
||||
(pin M3 0 none 0 9 0)
|
||||
)
|
||||
(logical_part R
|
||||
(pin 1 0 none 1 1 0)
|
||||
(pin 2 0 none 1 2 0)
|
||||
)
|
||||
(logical_part HEADER_20X2
|
||||
(pin 1 0 none 1 1 0)
|
||||
(pin 2 0 none 1 2 0)
|
||||
(pin 3 0 none 1 3 0)
|
||||
(pin 4 0 none 1 4 0)
|
||||
(pin 5 0 none 1 5 0)
|
||||
(pin 6 0 none 1 6 0)
|
||||
(pin 7 0 none 1 7 0)
|
||||
(pin 8 0 none 1 8 0)
|
||||
(pin 9 0 none 1 9 0)
|
||||
(pin 10 0 none 1 10 0)
|
||||
(pin 11 0 none 1 11 0)
|
||||
(pin 12 0 none 1 12 0)
|
||||
(pin 13 0 none 1 13 0)
|
||||
(pin 14 0 none 1 14 0)
|
||||
(pin 15 0 none 1 15 0)
|
||||
(pin 16 0 none 1 16 0)
|
||||
(pin 17 0 none 1 17 0)
|
||||
(pin 18 0 none 1 18 0)
|
||||
(pin 19 0 none 1 19 0)
|
||||
(pin 20 0 none 1 20 0)
|
||||
(pin 21 0 none 1 21 0)
|
||||
(pin 22 0 none 1 22 0)
|
||||
(pin 23 0 none 1 23 0)
|
||||
(pin 24 0 none 1 24 0)
|
||||
(pin 25 0 none 1 25 0)
|
||||
(pin 26 0 none 1 26 0)
|
||||
(pin 27 0 none 1 27 0)
|
||||
(pin 28 0 none 1 28 0)
|
||||
(pin 29 0 none 1 29 0)
|
||||
(pin 30 0 none 1 30 0)
|
||||
(pin 31 0 none 1 31 0)
|
||||
(pin 32 0 none 1 32 0)
|
||||
(pin 33 0 none 1 33 0)
|
||||
(pin 34 0 none 1 34 0)
|
||||
(pin 35 0 none 1 35 0)
|
||||
(pin 36 0 none 1 36 0)
|
||||
(pin 37 0 none 1 37 0)
|
||||
(pin 38 0 none 1 38 0)
|
||||
(pin 39 0 none 1 39 0)
|
||||
(pin 40 0 none 1 40 0)
|
||||
)
|
||||
(logical_part HEADER_4
|
||||
(pin 1 0 none 1 1 0)
|
||||
(pin 2 0 none 1 2 0)
|
||||
(pin 3 0 none 1 3 0)
|
||||
(pin 4 0 none 1 4 0)
|
||||
)
|
||||
(logical_part_mapping HEADER_20X2(comp J1))
|
||||
(logical_part_mapping HEADER_2(comp J2))
|
||||
(logical_part_mapping HEADER_4(comp J3))
|
||||
(logical_part_mapping HEADER_4(comp J4))
|
||||
(logical_part_mapping 'M-DIN_6-R'(comp JS1))
|
||||
(logical_part_mapping 'M-DIN_6-R'(comp JS2))
|
||||
(logical_part_mapping R(comp R1))
|
||||
(logical_part_mapping R(comp R2))
|
||||
(logical_part_mapping R(comp R3))
|
||||
(logical_part_mapping R(comp R4))
|
||||
(logical_part_mapping R(comp R5))
|
||||
(logical_part_mapping R(comp R6))
|
||||
(logical_part_mapping R(comp R7))
|
||||
(logical_part_mapping R(comp R8))
|
||||
)
|
||||
(network
|
||||
(net 0
|
||||
(pins JS1-3 JS2-3 J1-1)
|
||||
(rule(width 1.00000))
|
||||
)
|
||||
(net 5V
|
||||
(pins JS2-4 R6-2 R7-2 R5-2 JS1-4 R8-2 J2-2)
|
||||
(rule(width 1.00000))
|
||||
)
|
||||
(net N00391
|
||||
(pins R7-1 JS2-1 R3-2)
|
||||
)
|
||||
(net N00400
|
||||
(pins JS1-1 R5-1 R1-2)
|
||||
)
|
||||
(net N00414
|
||||
(pins JS1-5 R2-2 R6-1)
|
||||
)
|
||||
(net N00433
|
||||
(pins R4-2 JS2-5 R8-1)
|
||||
)
|
||||
(net PS2_CLK1
|
||||
(pins R2-1 J1-5)
|
||||
)
|
||||
(net PS2_CLK2
|
||||
(pins J1-9 R4-1)
|
||||
)
|
||||
(net PS2_DATA1
|
||||
(pins R1-1 J1-3)
|
||||
)
|
||||
(net PS2_DATA2
|
||||
(pins J1-7 R3-1)
|
||||
)
|
||||
)
|
||||
(wiring
|
||||
(wire(path BOTTOM 1.00000 -128.64721 11.30899 -128.64721 7.14721
|
||||
-126.00000 4.50000 -111.00000 4.50000 -108.24721 7.25279
|
||||
-108.24721 11.30899)
|
||||
(net 0)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path BOTTOM 1.00000 -67.80000 58.40000 -75.10000 58.40000
|
||||
-100.50000 33.00000 -100.50000 19.05620 -108.24721 11.30899)
|
||||
(net 0)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -114.95279 11.30899 -117.44380 13.80000
|
||||
-120.97451 13.80000)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -120.97451 13.80000 -120.97451 20.45098
|
||||
-120.82549 20.60000)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -138.40000 23.22549 -142.50000 27.32549
|
||||
-142.50000 18.45620 -135.35279 11.30899)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -135.35279 11.30899 -135.35279 6.35279
|
||||
-133.50000 4.50000 -124.50000 4.50000 -120.97451 8.02549
|
||||
-120.97451 13.80000)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -107.00000 23.22549 -102.72549 23.22549
|
||||
-96.00000 16.50000 -96.00000 12.00000 -103.50000 4.50000
|
||||
-124.50000 4.50000 -120.97451 8.02549 -120.97451 13.80000)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 1.00000 -92.40000 78.06000 -92.40000 74.10000
|
||||
-94.50000 72.00000 -121.50000 72.00000 -142.50000 51.00000
|
||||
-142.50000 27.32549 -138.40000 23.22549)
|
||||
(net 5V)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -119.17451 20.60000 -119.17451 20.17889
|
||||
-110.30461 11.30899)
|
||||
(net N00391)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -110.30461 11.30899 -112.42549 13.42987
|
||||
-112.42549 52.40000)
|
||||
(net N00391)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -130.70461 11.30899 -138.40000 19.00438
|
||||
-138.40000 21.57451)
|
||||
(net N00400)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -130.70461 11.30899 -130.70461 56.32088
|
||||
-130.62549 56.40000)
|
||||
(net N00400)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -128.64721 13.79819 -128.64721 54.37828
|
||||
-128.62549 54.40000)
|
||||
(net N00414)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -128.64721 13.79819 -128.64540 13.80000
|
||||
-122.62549 13.80000)
|
||||
(net N00414)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -110.22549 50.40000 -110.24721 50.37828
|
||||
-110.24721 15.79819 -108.24721 13.79819)
|
||||
(net N00433)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -108.24721 13.79819 -107.00000 15.04540
|
||||
-107.00000 21.57451)
|
||||
(net N00433)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -110.22549 50.40000 -110.10000 50.40000)
|
||||
(net N00433)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -126.97451 54.40000 -67.81221 54.40000
|
||||
-67.80000 54.41221)
|
||||
(net PS2_CLK1)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -67.80000 50.39900 -67.80100 50.40000
|
||||
-108.57451 50.40000)
|
||||
(net PS2_CLK2)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -128.97451 56.40000 -98.97451 56.40000
|
||||
-98.96792 56.39341 -67.80000 56.39341)
|
||||
(net PS2_DATA1)
|
||||
(type normal)
|
||||
)
|
||||
(wire(path TOP 0.25400 -67.80000 52.40561 -88.56890 52.40561
|
||||
-88.57451 52.40000 -110.77451 52.40000)
|
||||
(net PS2_DATA2)
|
||||
(type normal)
|
||||
)
|
||||
)
|
||||
(colors
|
||||
(color 0 color0 0 0 0)
|
||||
(color 1 color1 255 255 0)
|
||||
(color 2 color2 0 255 255)
|
||||
(color 3 color3 255 0 0)
|
||||
(color 4 color4 127 127 127)
|
||||
(color 5 color5 0 127 0)
|
||||
(color 6 color6 0 255 0)
|
||||
(color 7 color7 0 0 255)
|
||||
(color 8 color8 255 0 255)
|
||||
(color 9 color9 127 0 0)
|
||||
(color 10 color10 0 0 127)
|
||||
(color 11 color11 127 0 127)
|
||||
(color 12 color12 127 127 0)
|
||||
(color 13 color13 0 127 127)
|
||||
(color 14 color14 255 255 255)
|
||||
(color 15 color15 0 255 0)
|
||||
(color 16 color16 0 127 0)
|
||||
(color 17 color17 0 127 127)
|
||||
(color 18 black 0 0 0)
|
||||
(set_color background color0)
|
||||
(set_color highlight color14)
|
||||
(set_color signal 1 color2)
|
||||
(set_color power 2 color4)
|
||||
(set_color power 3 color5)
|
||||
(set_color signal 15 color3)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Layout to SPECCTRA Version 10.5.0
|
||||
Copyright 1985-2005 Cadence Design Systems, Inc.
|
||||
|
||||
Translate time 0 seconds
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,991 @@
|
|||
*
|
||||
G04 Mass Parameters ***
|
||||
*
|
||||
G04 Image ***
|
||||
*
|
||||
%INC:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.DRD*%
|
||||
%ICAS*%
|
||||
%MOIN*%
|
||||
%IPPOS*%
|
||||
%ASAXBY*%
|
||||
G74*%FSLAN2X34Y34*%
|
||||
*
|
||||
G04 Aperture Definitions ***
|
||||
*
|
||||
%ADD10C,0.0531*%
|
||||
%ADD11C,0.0620*%
|
||||
%ADD12R,0.0620X0.0620*%
|
||||
%ADD13C,0.0550*%
|
||||
%ADD14R,0.0550X0.0550*%
|
||||
%ADD15C,0.1120*%
|
||||
%ADD16R,0.0350X0.0300*%
|
||||
%ADD17R,0.0300X0.0350*%
|
||||
%ADD18C,0.3150X0.1575*%
|
||||
%ADD19C,0.0004*%
|
||||
%ADD20C,0.0100*%
|
||||
%ADD21C,0.0394*%
|
||||
%ADD22C,0.0531*%
|
||||
%ADD23C,0.0620*%
|
||||
%ADD24R,0.0620X0.0620*%
|
||||
%ADD25C,0.0550*%
|
||||
%ADD26R,0.0550X0.0550*%
|
||||
%ADD27C,0.1120*%
|
||||
%ADD28C,0.3150X0.1575*%
|
||||
%ADD29C,0.0640*%
|
||||
%ADD30C,0.0820*%
|
||||
%ADD31R,0.0820X0.0820*%
|
||||
%ADD32C,0.0750*%
|
||||
%ADD33R,0.0750X0.0750*%
|
||||
%ADD34C,0.1320*%
|
||||
%ADD35C,0.1181*%
|
||||
%ADD36C,0.0079*%
|
||||
%ADD37C,0.0600*%
|
||||
%ADD38R,0.0400X0.0350*%
|
||||
%ADD39R,0.0350X0.0400*%
|
||||
%ADD40C,0.3150*%
|
||||
%ADD41C,0.0080*%
|
||||
%ADD42C,0.0060*%
|
||||
%ADD43C,0.0000*%
|
||||
%ADD44C,0.1181*%
|
||||
%ADD45C,0.0040*%
|
||||
%ADD46C,0.0050*%
|
||||
*
|
||||
G04 Plot Data ***
|
||||
*
|
||||
G54D20*
|
||||
G01X0024708Y-0011333D02*
|
||||
X0024042D01*
|
||||
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|
||||
Y-0010500D01*
|
||||
X0024625Y-0010333D01*
|
||||
X0024125D01*
|
||||
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|
||||
X0023258Y-0011333D02*
|
||||
X0023758Y-0010333D01*
|
||||
X0023092D01*
|
||||
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|
||||
X0011729D01*
|
||||
Y-0010333D01*
|
||||
X0011446Y-0011000D02*
|
||||
X0010779D01*
|
||||
X0011446Y-0011333D02*
|
||||
Y-0010833D01*
|
||||
X0011196Y-0010333D01*
|
||||
X0011029D01*
|
||||
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|
||||
Y-0011333D01*
|
||||
X0010162D02*
|
||||
Y-0010333D01*
|
||||
X0010496D02*
|
||||
X0009829D01*
|
||||
X0008962Y-0011333D02*
|
||||
X0008879Y-0011167D01*
|
||||
Y-0010500D01*
|
||||
X0008962Y-0010333D01*
|
||||
X0009462D01*
|
||||
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|
||||
Y-0011167D01*
|
||||
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|
||||
X0008962D01*
|
||||
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|
||||
Y-0010333D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0024597D01*
|
||||
Y-0009472D01*
|
||||
X0010869D02*
|
||||
Y-0009139D01*
|
||||
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|
||||
Y-0009139D01*
|
||||
X0011036Y-0009028D01*
|
||||
X0010925D01*
|
||||
X0010869Y-0009139D01*
|
||||
X0010814Y-0009028D01*
|
||||
X0010703D01*
|
||||
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|
||||
Y-0009472D01*
|
||||
X0010169D02*
|
||||
Y-0009139D01*
|
||||
X0010392Y-0009472D02*
|
||||
Y-0009139D01*
|
||||
X0010336Y-0009028D01*
|
||||
X0010225D01*
|
||||
X0010169Y-0009139D01*
|
||||
X0010114Y-0009028D01*
|
||||
X0010003D01*
|
||||
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|
||||
Y-0009472D01*
|
||||
X0008464D02*
|
||||
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|
||||
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|
||||
Y-0009028D01*
|
||||
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|
||||
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|
||||
X0008575D01*
|
||||
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|
||||
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|
||||
Y-0009250D01*
|
||||
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|
||||
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|
||||
X0008464D01*
|
||||
X0007764D02*
|
||||
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|
||||
X0007597Y-0009250D01*
|
||||
Y-0009028D01*
|
||||
X0007653Y-0008917D01*
|
||||
X0007764Y-0008806D01*
|
||||
X0007875D01*
|
||||
X0007986Y-0008917D01*
|
||||
X0008042Y-0009028D01*
|
||||
Y-0009250D01*
|
||||
X0007986Y-0009361D01*
|
||||
X0007875Y-0009472D01*
|
||||
X0007764D01*
|
||||
X0007064D02*
|
||||
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|
||||
X0006897Y-0009250D01*
|
||||
Y-0009028D01*
|
||||
X0006953Y-0008917D01*
|
||||
X0007064Y-0008806D01*
|
||||
X0007175D01*
|
||||
X0007286Y-0008917D01*
|
||||
X0007342Y-0009028D01*
|
||||
Y-0009250D01*
|
||||
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|
||||
X0007175Y-0009472D01*
|
||||
X0007064D01*
|
||||
X0006531D02*
|
||||
X0006642D01*
|
||||
Y-0009361D01*
|
||||
X0006531D01*
|
||||
Y-0009472D01*
|
||||
X0005719Y-0009361D02*
|
||||
X0005831Y-0009472D01*
|
||||
X0006053D01*
|
||||
X0006164Y-0009361D01*
|
||||
Y-0009250D01*
|
||||
X0005942Y-0009028D01*
|
||||
X0006164Y-0008806D01*
|
||||
X0005719D01*
|
||||
X0024319Y-0007639D02*
|
||||
X0024653D01*
|
||||
X0024708Y-0007750D01*
|
||||
Y-0007861D01*
|
||||
X0024653Y-0007972D01*
|
||||
X0024319D01*
|
||||
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|
||||
Y-0007750D01*
|
||||
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|
||||
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||||
Y-0007639D01*
|
||||
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|
||||
Y-0007639D01*
|
||||
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|
||||
X0010925D01*
|
||||
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|
||||
X0010814Y-0007528D01*
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||||
X0010703D01*
|
||||
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|
||||
Y-0007972D01*
|
||||
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|
||||
Y-0007639D01*
|
||||
X0010392Y-0007972D02*
|
||||
Y-0007639D01*
|
||||
X0010336Y-0007528D01*
|
||||
X0010225D01*
|
||||
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|
||||
X0010114Y-0007528D01*
|
||||
X0010003D01*
|
||||
X0009947Y-0007639D01*
|
||||
Y-0007972D01*
|
||||
X0008742D02*
|
||||
X0008519D01*
|
||||
X0008631D02*
|
||||
Y-0007306D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
Y-0007306D01*
|
||||
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||||
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||||
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|
||||
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Y-0007750D01*
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||||
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||||
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Y-0007972D01*
|
||||
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|
||||
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|
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||||
Y-0007417D01*
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Y-0005917D01*
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Y-0006139D01*
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Y-0006139D01*
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||||
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Y-0006472D01*
|
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||||
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|
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|
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
Y-0004972D01*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
Y-0004972D01*
|
||||
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|
||||
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|
||||
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|
||||
Y-0004861D01*
|
||||
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|
||||
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|
||||
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|
||||
Y-0004750D01*
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*
|
||||
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|
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*
|
||||
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|
||||
X-0036378Y0030732D03*
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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|
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|
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|
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||||
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|
||||
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|
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|
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|
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|
||||
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|
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||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
X-0046919Y0008110D03*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X-0050640D03*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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M02*
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,203 @@
|
|||
Post Processor Report
|
||||
OrCAD FILE: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.MAX
|
||||
Fri Sep 17 14:14:27 2010
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.TOP
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.TOP:
|
||||
---------------------------------------------------------
|
||||
D10: 0.0531 ROUND -- 0 Draws, 40 Flashes
|
||||
D11: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
D12: 0.0620 SQUARE -- 0 Draws, 1 Flashes
|
||||
D13: 0.0550 ROUND -- 0 Draws, 16 Flashes
|
||||
D14: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D15: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D16: 0.0350 x 0.0300 RECTANGLE ----- 12 Flashes
|
||||
D17: 0.0300 x 0.0350 RECTANGLE ----- 4 Flashes
|
||||
D18: 0.3150 OD, 0.2910 ID ANNULAR -- 4 Flashes
|
||||
D19: 0.0004 ROUND -- 123100 Draws, 0 Flashes
|
||||
D20: 0.0100 ROUND -- 28 Draws, 0 Flashes
|
||||
D21: 0.0394 ROUND -- 25 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
12 D-Codes ----- 123153 Draws, 88 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.BOT
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.BOT:
|
||||
---------------------------------------------------------
|
||||
D19: 0.0004 ROUND -- 65997 Draws, 0 Flashes
|
||||
D21: 0.0394 ROUND -- 9 Draws, 0 Flashes
|
||||
D22: 0.0531 ROUND -- 0 Draws, 40 Flashes
|
||||
D23: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
D24: 0.0620 SQUARE -- 0 Draws, 1 Flashes
|
||||
D25: 0.0550 ROUND -- 0 Draws, 16 Flashes
|
||||
D26: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D27: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D28: 0.3150 OD, 0.2910 ID ANNULAR -- 4 Flashes
|
||||
---------------------------------------------------------
|
||||
9 D-Codes ----- 66006 Draws, 72 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.GND
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.GND:
|
||||
---------------------------------------------------------
|
||||
D29: 0.0640 ROUND -- 0 Draws, 40 Flashes
|
||||
D30: 0.0820 ROUND -- 0 Draws, 1 Flashes
|
||||
D31: 0.0820 SQUARE -- 0 Draws, 1 Flashes
|
||||
D32: 0.0750 ROUND -- 0 Draws, 16 Flashes
|
||||
D33: 0.0750 SQUARE -- 0 Draws, 4 Flashes
|
||||
D34: 0.1320 ROUND -- 0 Draws, 6 Flashes
|
||||
D35: 0.1181 ROUND -- 0 Draws, 4 Flashes
|
||||
D36: 0.0079 ROUND -- 4 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
8 D-Codes ----- 4 Draws, 72 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.PWR
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.PWR:
|
||||
---------------------------------------------------------
|
||||
D29: 0.0640 ROUND -- 0 Draws, 40 Flashes
|
||||
D30: 0.0820 ROUND -- 0 Draws, 1 Flashes
|
||||
D31: 0.0820 SQUARE -- 0 Draws, 1 Flashes
|
||||
D32: 0.0750 ROUND -- 0 Draws, 16 Flashes
|
||||
D33: 0.0750 SQUARE -- 0 Draws, 4 Flashes
|
||||
D34: 0.1320 ROUND -- 0 Draws, 6 Flashes
|
||||
D35: 0.1181 ROUND -- 0 Draws, 4 Flashes
|
||||
D36: 0.0079 ROUND -- 4 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
8 D-Codes ----- 4 Draws, 72 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SMT
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SMT:
|
||||
---------------------------------------------------------
|
||||
D23: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
D24: 0.0620 SQUARE -- 0 Draws, 1 Flashes
|
||||
D25: 0.0550 ROUND -- 0 Draws, 16 Flashes
|
||||
D26: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D27: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D37: 0.0600 ROUND -- 0 Draws, 40 Flashes
|
||||
D38: 0.0400 x 0.0350 RECTANGLE ----- 12 Flashes
|
||||
D39: 0.0350 x 0.0400 RECTANGLE ----- 4 Flashes
|
||||
D40: 0.3150 ROUND -- 0 Draws, 4 Flashes
|
||||
---------------------------------------------------------
|
||||
9 D-Codes ----- 0 Draws, 88 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SMB
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SMB:
|
||||
---------------------------------------------------------
|
||||
D23: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
D24: 0.0620 SQUARE -- 0 Draws, 1 Flashes
|
||||
D25: 0.0550 ROUND -- 0 Draws, 16 Flashes
|
||||
D26: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D27: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D37: 0.0600 ROUND -- 0 Draws, 40 Flashes
|
||||
D40: 0.3150 ROUND -- 0 Draws, 4 Flashes
|
||||
---------------------------------------------------------
|
||||
7 D-Codes ----- 0 Draws, 72 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SST
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.SST:
|
||||
---------------------------------------------------------
|
||||
D20: 0.0100 ROUND -- 429 Draws, 0 Flashes
|
||||
D36: 0.0079 ROUND -- 29 Draws, 0 Flashes
|
||||
D41: 0.0080 ROUND -- 53 Draws, 0 Flashes
|
||||
D42: 0.0060 ROUND -- 281 Draws, 0 Flashes
|
||||
D43: 0.0000 ROUND -- 12 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
5 D-Codes ----- 804 Draws, 0 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.AST
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.AST:
|
||||
---------------------------------------------------------
|
||||
D23: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
D24: 0.0620 SQUARE -- 0 Draws, 1 Flashes
|
||||
D25: 0.0550 ROUND -- 0 Draws, 16 Flashes
|
||||
D26: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D27: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D36: 0.0079 ROUND -- 4 Draws, 0 Flashes
|
||||
D41: 0.0080 ROUND -- 116 Draws, 0 Flashes
|
||||
D42: 0.0060 ROUND -- 372 Draws, 0 Flashes
|
||||
D44: 0.1181 ROUND -- 0 Draws, 4 Flashes
|
||||
D45: 0.0040 ROUND -- 60 Draws, 0 Flashes
|
||||
D46: 0.0050 ROUND -- 265 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
11 D-Codes ----- 817 Draws, 32 Flashes
|
||||
|
||||
*********************************************************
|
||||
|
||||
Output file: C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.DRD
|
||||
|
||||
Aperture totals for C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2-6.DRD:
|
||||
---------------------------------------------------------
|
||||
D20: 0.0100 ROUND -- 621 Draws, 0 Flashes
|
||||
D36: 0.0079 ROUND -- 4 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
2 D-Codes ----- 625 Draws, 0 Flashes
|
||||
|
||||
|
||||
*********************************************************
|
||||
|
||||
Aperture totals for entire project:
|
||||
---------------------------------------------------------
|
||||
D10: 0.0531 ROUND -- 0 Draws, 40 Flashes
|
||||
D11: 0.0620 ROUND -- 0 Draws, 1 Flashes
|
||||
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|
||||
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|
||||
D14: 0.0550 SQUARE -- 0 Draws, 4 Flashes
|
||||
D15: 0.1120 ROUND -- 0 Draws, 6 Flashes
|
||||
D16: 0.0350 x 0.0300 RECTANGLE ----- 12 Flashes
|
||||
D17: 0.0300 x 0.0350 RECTANGLE ----- 4 Flashes
|
||||
D18: 0.3150 OD, 0.2910 ID ANNULAR -- 4 Flashes
|
||||
D19: 0.0004 ROUND -- 189097 Draws, 0 Flashes
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
D34: 0.1320 ROUND -- 0 Draws, 12 Flashes
|
||||
D35: 0.1181 ROUND -- 0 Draws, 8 Flashes
|
||||
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|
||||
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|
||||
D38: 0.0400 x 0.0350 RECTANGLE ----- 12 Flashes
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
D46: 0.0050 ROUND -- 265 Draws, 0 Flashes
|
||||
---------------------------------------------------------
|
||||
37 D-Codes ----- 191413 Draws, 496 Flashes
|
||||
|
||||
|
||||
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|
||||
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(DeviceIndex "0"))
|
||||
("HEADER 2"
|
||||
(FullPartName "HEADER 2.Normal")
|
||||
(LibraryName "C:\ORCAD\ORCAD_10.5\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(R
|
||||
(FullPartName "R.Normal")
|
||||
(LibraryName
|
||||
"C:\ORCAD\ORCAD_10.5\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB")
|
||||
(DeviceIndex "0"))
|
||||
("HEADER 3"
|
||||
(FullPartName "HEADER 3.Normal")
|
||||
(LibraryName "C:\ORCAD\ORCAD_10.5\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(M-DIN_6-R
|
||||
(FullPartName "M-DIN_6-R.Normal")
|
||||
(LibraryName "C:\ORCAD\ORCAD_10.5\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
|
||||
(DeviceIndex "0"))
|
||||
("HEADER 20X2"
|
||||
(FullPartName "HEADER 20X2.Normal")
|
||||
(LibraryName "C:\ORCAD\ORCAD_10.5\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(C
|
||||
(FullPartName "C.Normal")
|
||||
(LibraryName "..\..\LIBRARY\PSPICE\ANALOG.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(L
|
||||
(FullPartName "L.Normal")
|
||||
(LibraryName "..\..\LIBRARY\PSPICE\ANALOG.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(VSTIM
|
||||
(FullPartName "VSTIM.Normal")
|
||||
(LibraryName "..\..\LIBRARY\PSPICE\SOURCSTM.OLB")
|
||||
(DeviceIndex "0"))
|
||||
(VDC
|
||||
(FullPartName "VDC.Normal")
|
||||
(LibraryName "..\..\LIBRARY\PSPICE\SOURCE.OLB")
|
||||
(DeviceIndex "0")))
|
||||
(LastUsedLibraryBrowseDirectory "C:\OrCAD\OrCAD_10.5\tools\capture\library")
|
||||
(MPSSessionName "BlueDeep")
|
||||
(GlobalState
|
||||
(FileView
|
||||
(Path "Design Resources")
|
||||
(Path "Outputs"))
|
||||
(HierarchyView)
|
||||
(Doc
|
||||
(Type "COrCapturePMDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 160 611 -4 -30 0 200 0 431"))
|
||||
(Tab 0))
|
||||
(Doc
|
||||
(Type "COrSchematicDoc")
|
||||
(Frame
|
||||
(Placement "44 2 3 -1 -1 -4 -30 44 1170 58 497")
|
||||
(Scroll "0 0")
|
||||
(Zoom "100")
|
||||
(Occurrence "/"))
|
||||
(Path
|
||||
"C:\DOCUMENTS AND SETTINGS\BLUEDEEP\MIS DOCUMENTOS\ORCAD\CONECTOR_PS2\NUEVA CARPETA\PS2.DSN")
|
||||
(Schematic "SCHEMATIC1")
|
||||
(Page "PAGE1"))))
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,28 @@
|
|||
EXTRA_CFLAGS += -Wall
|
||||
OPENWRT_BASE = /home/ari/sie/p/openwrt-xburst
|
||||
KERNEL_SRC = $(OPENWRT_BASE)/build_dir/linux-xburst_qi_lb60/linux-2.6.32.16/
|
||||
CC = $(OPENWRT_BASE)/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.32/usr/bin/mipsel-openwrt-linux-gcc
|
||||
CROSS_COMPILE = $(OPENWRT_BASE)/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.32/usr/bin/mipsel-openwrt-linux-
|
||||
NANO_IP = 192.168.254.101
|
||||
|
||||
obj-m += ps2_kb.o ps2_ms.o#hello.o memory.o digTest.o
|
||||
all: driver #main
|
||||
|
||||
driver:
|
||||
make -C $(KERNEL_SRC) M=$(PWD) ARCH=mips CROSS_COMPILE=$(CROSS_COMPILE) modules
|
||||
clean:
|
||||
make -C $(KERNEL_SRC) M=$(PWD) ARCH=mips CROSS_COMPILE=$(CROSS_COMPILE) clean
|
||||
rm -f *.o Modules.symvers
|
||||
|
||||
cleanall:
|
||||
make -C $(KERNEL_SRC) M=$(PWD) ARCH=mips CROSS_COMPILE=$(CROSS_COMPILE) clean
|
||||
rm -f *.o *.c~ Makefile~ main.o main Modules.symvers
|
||||
|
||||
upload: all
|
||||
scp ps2_ms.ko root@$(NANO_IP):~/
|
||||
|
||||
main: main.o
|
||||
|
||||
PREPROCESS.c = $(CC) $(CFLAGS) $(TARGET_ARCH) -E -Wp,-C,-dD,-dI
|
||||
%.pp : %.c FORCE
|
||||
$(PREPROCESS.c) $< > $@
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Necessary includes for drivers */
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h> /* printk() */
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
static int hello_init(void) {
|
||||
printk("Hello world!. init\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hello_exit(void) {
|
||||
printk("Bye, cruel world. exit\n");
|
||||
}
|
||||
|
||||
module_init(hello_init);
|
||||
module_exit(hello_exit)
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* drivers/input/keyboard/hpps2atkbd.h
|
||||
*
|
||||
* Copyright (c) 2004 Helge Deller <deller@gmx.de>
|
||||
* Copyright (c) 2002 Laurent Canet <canetl@esiee.fr>
|
||||
* Copyright (c) 2002 Thibaut Varene <varenet@parisc-linux.org>
|
||||
* Copyright (c) 2000 Xavier Debacker <debackex@esiee.fr>
|
||||
*
|
||||
* HP PS/2 AT-compatible Keyboard, found in PA/RISC Workstations & Laptops
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
|
||||
/* Is the keyboard an RDI PrecisionBook? */
|
||||
#ifndef CONFIG_KEYBOARD_ATKBD_RDI_KEYCODES
|
||||
# define CONFLICT(x,y) x
|
||||
#else
|
||||
# define CONFLICT(x,y) y
|
||||
#endif
|
||||
|
||||
/* sadly RDI (Tadpole) decided to ship a different keyboard layout
|
||||
than HP for their PS/2 laptop keyboard which leads to conflicting
|
||||
keycodes between a normal HP PS/2 keyboard and a RDI Precisionbook.
|
||||
HP: RDI: */
|
||||
#define C_07 CONFLICT( KEY_F12, KEY_F1 )
|
||||
#define C_11 CONFLICT( KEY_LEFTALT, KEY_LEFTCTRL )
|
||||
#define C_14 CONFLICT( KEY_LEFTCTRL, KEY_CAPSLOCK )
|
||||
#define C_58 CONFLICT( KEY_CAPSLOCK, KEY_RIGHTCTRL )
|
||||
#define C_61 CONFLICT( KEY_102ND, KEY_LEFT )
|
||||
|
||||
/* Raw SET 2 scancode table */
|
||||
|
||||
/* 00 */ KEY_RESERVED, KEY_F9, KEY_RESERVED, KEY_F5, KEY_F3, KEY_F1, KEY_F2, C_07,
|
||||
/* 08 */ KEY_ESC, KEY_F10, KEY_F8, KEY_F6, KEY_F4, KEY_TAB, KEY_GRAVE, KEY_F2,
|
||||
/* 10 */ KEY_RESERVED, C_11, KEY_LEFTSHIFT, KEY_RESERVED, C_14, KEY_Q, KEY_1, KEY_F3,
|
||||
/* 18 */ KEY_RESERVED, KEY_LEFTALT, KEY_Z, KEY_S, KEY_A, KEY_W, KEY_2, KEY_F4,
|
||||
/* 20 */ KEY_RESERVED, KEY_C, KEY_X, KEY_D, KEY_E, KEY_4, KEY_3, KEY_F5,
|
||||
/* 28 */ KEY_RESERVED, KEY_SPACE, KEY_V, KEY_F, KEY_T, KEY_R, KEY_5, KEY_F6,
|
||||
/* 30 */ KEY_RESERVED, KEY_N, KEY_B, KEY_H, KEY_G, KEY_Y, KEY_6, KEY_F7,
|
||||
/* 38 */ KEY_RESERVED, KEY_RIGHTALT, KEY_M, KEY_J, KEY_U, KEY_7, KEY_8, KEY_F8,
|
||||
/* 40 */ KEY_RESERVED, KEY_COMMA, KEY_K, KEY_I, KEY_O, KEY_0, KEY_9, KEY_F9,
|
||||
/* 48 */ KEY_RESERVED, KEY_DOT, KEY_SLASH, KEY_L, KEY_SEMICOLON, KEY_P, KEY_MINUS, KEY_F10,
|
||||
/* 50 */ KEY_RESERVED, KEY_RESERVED, KEY_APOSTROPHE,KEY_RESERVED, KEY_LEFTBRACE, KEY_EQUAL, KEY_F11, KEY_SYSRQ,
|
||||
/* 58 */ C_58, KEY_RIGHTSHIFT,KEY_ENTER, KEY_RIGHTBRACE,KEY_BACKSLASH, KEY_BACKSLASH,KEY_F12, KEY_SCROLLLOCK,
|
||||
/* 60 */ KEY_DOWN, C_61, KEY_PAUSE, KEY_UP, KEY_DELETE, KEY_END, KEY_BACKSPACE, KEY_INSERT,
|
||||
/* 68 */ KEY_RESERVED, KEY_KP1, KEY_RIGHT, KEY_KP4, KEY_KP7, KEY_PAGEDOWN, KEY_HOME, KEY_PAGEUP,
|
||||
/* 70 */ KEY_KP0, KEY_KPDOT, KEY_KP2, KEY_KP5, KEY_KP6, KEY_KP8, KEY_ESC, KEY_NUMLOCK,
|
||||
/* 78 */ KEY_F11, KEY_KPPLUS, KEY_KP3, KEY_KPMINUS, KEY_KPASTERISK,KEY_KP9, KEY_SCROLLLOCK,KEY_102ND,
|
||||
/* 80 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 88 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 90 */ KEY_RESERVED, KEY_RIGHTALT, 255, KEY_RESERVED, KEY_RIGHTCTRL, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 98 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_CAPSLOCK, KEY_RESERVED, KEY_LEFTMETA,
|
||||
/* a0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RIGHTMETA,
|
||||
/* a8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_COMPOSE,
|
||||
/* b0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* b8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* c0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* c8 */ KEY_RESERVED, KEY_RESERVED, KEY_KPSLASH, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* d0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* d8 */ KEY_RESERVED, KEY_RESERVED, KEY_KPENTER, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* e0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* e8 */ KEY_RESERVED, KEY_END, KEY_RESERVED, KEY_LEFT, KEY_HOME, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* f0 */ KEY_INSERT, KEY_DELETE, KEY_DOWN, KEY_RESERVED, KEY_RIGHT, KEY_UP, KEY_RESERVED, KEY_PAUSE,
|
||||
/* f8 */ KEY_RESERVED, KEY_RESERVED, KEY_PAGEDOWN, KEY_RESERVED, KEY_SYSRQ, KEY_PAGEUP, KEY_RESERVED, KEY_RESERVED,
|
||||
|
||||
/* These are offset for escaped keycodes: */
|
||||
|
||||
/* 00 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_F7, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 08 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_LEFTMETA, KEY_RIGHTMETA, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 10 */ KEY_RESERVED, KEY_RIGHTALT, KEY_RESERVED, KEY_RESERVED, KEY_RIGHTCTRL, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 18 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 20 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 28 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 30 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 38 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 40 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 48 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 50 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 58 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 60 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 68 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 70 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 78 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 80 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 88 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 90 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* 98 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* a0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* a8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* b0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* b8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* c0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* c8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* d0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* d8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* e0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* e8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* f0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
|
||||
/* f8 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED
|
||||
|
||||
#undef CONFLICT
|
||||
#undef C_07
|
||||
#undef C_11
|
||||
#undef C_14
|
||||
#undef C_58
|
||||
#undef C_61
|
||||
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Driver preliminar y de pruebas de teclado ps2 kbps2
|
||||
*
|
||||
* Author: Ari Andrés Bejarano H.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h> /* Needed by all modules */
|
||||
#include <linux/kernel.h> /* Needed for KERN_INFO, printk() */
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/interrupt.h> /* We want an interrupt */
|
||||
#include <linux/irq.h> /* We want an interrupt */
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/fs.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h> /*ioremap ioremap_nocache iounmap iowriteXX ioreadXX*/
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-jz4740/gpio.h>
|
||||
#include<asm/system.h> /*rmb*/
|
||||
|
||||
#define FPGA_IRQ_PIN JZ_GPIO_PORTC(15)
|
||||
#define FPGA_CS JZ_GPIO_PORTB(26)
|
||||
#define FPGA_BASE_BEGIN 0x15000000
|
||||
#define FPGA_BASE_END 0x17FFFFFF
|
||||
#define SUCCESS 0
|
||||
#define DEVICE_NAME "kbps2" /* Dev name as it appears in /proc/devices */
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Ari");
|
||||
MODULE_DESCRIPTION("Keyboard ps2");
|
||||
MODULE_VERSION("1.0");
|
||||
|
||||
/* Declaration of kbps2.c functions */
|
||||
static irqreturn_t irq_handler(int irq, void *dev_id);
|
||||
static int kbps2_open(struct inode *, struct file *);
|
||||
static int kbps2_release(struct inode *, struct file *);
|
||||
static ssize_t kbps2_read(struct file *, char *, size_t, loff_t *);
|
||||
static ssize_t kbps2_write(struct file *, const char *, size_t, loff_t *);
|
||||
static int __init kbps2_init(void);
|
||||
static void __exit kbps2_exit(void);
|
||||
|
||||
/* Structure that declares the usual file */
|
||||
/* access functions */
|
||||
struct file_operations fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.read = kbps2_read,
|
||||
.write = kbps2_write,
|
||||
.open = kbps2_open,
|
||||
.release = kbps2_release
|
||||
};
|
||||
|
||||
/* Declaration of the init and exit functions */
|
||||
module_init(kbps2_init);
|
||||
module_exit(kbps2_exit);
|
||||
|
||||
/* Global variables of the driver */
|
||||
static int irq_enabled = 0;
|
||||
static int is_device_open = 0; /* Is device open? Used to prevent multiple access to device */
|
||||
static int Major=65; /* Major number */
|
||||
static DECLARE_WAIT_QUEUE_HEAD(wq);
|
||||
static void __iomem *ioaddress;
|
||||
static unsigned int interrupt_counter = 0;
|
||||
|
||||
static int __init kbps2_init(void)
|
||||
{
|
||||
int res, irq, result;
|
||||
|
||||
barrier();
|
||||
|
||||
printk(KERN_INFO "FPGA module is Up.\n");
|
||||
interrupt_counter = 0;
|
||||
|
||||
/* Registering device */
|
||||
result = register_chrdev(Major, DEVICE_NAME, &fops);
|
||||
if (result < 0) {
|
||||
printk("<1>memory: cannot obtain major number %d\n", Major);
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Set up the FGPA irq line */
|
||||
irq = gpio_to_irq(FPGA_IRQ_PIN);
|
||||
res = request_irq(irq, irq_handler, IRQF_DISABLED | IRQF_TRIGGER_RISING, "FPGA - IRQ", NULL); // IRQF_TRIGGER_FALLING
|
||||
irq_enabled = 1;
|
||||
printk(KERN_INFO "FPGA irq_enabled...\n");
|
||||
|
||||
/* Set GPIOB26 as part of External Memory Controller*/
|
||||
jz_gpio_set_function (FPGA_CS, JZ_GPIO_FUNC_NONE);
|
||||
/* Use ioremap to get a handle on our region */
|
||||
ioaddress = __ioremap(FPGA_BASE_BEGIN, FPGA_BASE_END - FPGA_BASE_BEGIN, _CACHE_UNCACHED);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit kbps2_exit(void)
|
||||
{
|
||||
// int ret;
|
||||
/*Tho order for free_irq, iounmap & unregister is very important */
|
||||
free_irq(FPGA_IRQ_PIN, NULL);
|
||||
__iounmap(ioaddress);
|
||||
unregister_chrdev(Major, DEVICE_NAME);
|
||||
printk(KERN_INFO "FPGA driver is down...\n");
|
||||
}
|
||||
|
||||
static irqreturn_t irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
unsigned int red;
|
||||
if(irq_enabled)
|
||||
{
|
||||
interrupt_counter++;
|
||||
printk(KERN_INFO "interrupt_counter=%d\n",interrupt_counter);
|
||||
red=ioread32(ioaddress)& 0XFF;
|
||||
rmb();
|
||||
printk("%X \n", red);
|
||||
wake_up_interruptible(&wq);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int kbps2_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (is_device_open)
|
||||
return -EBUSY;
|
||||
|
||||
is_device_open = 1;
|
||||
|
||||
try_module_get(THIS_MODULE);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
static int kbps2_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
is_device_open = 0;
|
||||
|
||||
module_put(THIS_MODULE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t kbps2_read(struct file *filp, char *buffer, size_t count, loff_t *offset)
|
||||
{
|
||||
unsigned int red;
|
||||
|
||||
printk(KERN_INFO "read______-_-\n");
|
||||
red=ioread32(ioaddress)& 0XFF;
|
||||
rmb();
|
||||
printk("%X\n", red);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t kbps2_write(struct file *filp, const char *buff, size_t count, loff_t * off)
|
||||
{
|
||||
|
||||
printk(KERN_INFO "write______-_-\n");
|
||||
printk("%X\n", buff[0]);
|
||||
iowrite32(buff[0],ioaddress);
|
||||
wmb();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/* Necessary includes for drivers */
|
||||
#include <linux/init.h>
|
||||
//#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h> /* printk() */
|
||||
#include <linux/slab.h> /* kmalloc() */
|
||||
#include <linux/fs.h> /* everything... */
|
||||
#include <linux/errno.h> /* error codes */
|
||||
#include <linux/types.h> /* size_t */
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/fcntl.h> /* O_ACCMODE */
|
||||
#include <linux/ioport.h>
|
||||
#include <asm/system.h> /* cli(), *_flags */
|
||||
#include <asm/uaccess.h> /* copy_from/to_user */
|
||||
#include <asm/io.h> /* inb, outb */
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
/* Declaration of memory.c functions */
|
||||
int memory_open(struct inode *inode, struct file *filp);
|
||||
int memory_release(struct inode *inode, struct file *filp);
|
||||
ssize_t memory_read(struct file *filp, char *buf, size_t count, loff_t *f_pos);
|
||||
ssize_t memory_write(struct file *filp, char *buf, size_t count, loff_t *f_pos);
|
||||
void memory_exit(void);
|
||||
int memory_init(void);
|
||||
|
||||
/* Structure that declares the usual file */
|
||||
/* access functions */
|
||||
struct file_operations memory_fops = {
|
||||
read: memory_read,
|
||||
write: memory_write,
|
||||
open: memory_open,
|
||||
release: memory_release
|
||||
};
|
||||
|
||||
/* Declaration of the init and exit functions */
|
||||
module_init(memory_init);
|
||||
module_exit(memory_exit);
|
||||
|
||||
/* Global variables of the driver */
|
||||
/* Major number */
|
||||
int memory_major = 60;
|
||||
/* Buffer to store data */
|
||||
char *memory_buffer;
|
||||
|
||||
int memory_init(void) {
|
||||
|
||||
int result;
|
||||
|
||||
/* Registering device */
|
||||
result = register_chrdev(memory_major, "memory", &memory_fops);
|
||||
if (result < 0) {
|
||||
printk(
|
||||
"<1>memory: cannot obtain major number %d\n", memory_major);
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Allocating memory for the buffer */
|
||||
memory_buffer = kmalloc(1, GFP_KERNEL);
|
||||
if (!memory_buffer) {
|
||||
result = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
memset(memory_buffer, 0, 1);
|
||||
|
||||
printk("<1>Inserting memory module\n");
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
memory_exit();
|
||||
return result;
|
||||
}
|
||||
|
||||
void memory_exit(void) {
|
||||
/* Freeing the major number */
|
||||
unregister_chrdev(memory_major, "memory");
|
||||
|
||||
/* Freeing buffer memory */
|
||||
if (memory_buffer) {
|
||||
kfree(memory_buffer);
|
||||
}
|
||||
|
||||
printk("<1>Removing memory module\n");
|
||||
|
||||
}
|
||||
|
||||
int memory_open(struct inode *inode, struct file *filp) {
|
||||
|
||||
/* Success */
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
int memory_release(struct inode *inode, struct file *filp) {
|
||||
|
||||
/* Success */
|
||||
return 0;
|
||||
}
|
||||
|
||||
ssize_t memory_read(struct file *filp, char *buf,
|
||||
size_t count, loff_t *f_pos) {
|
||||
|
||||
/* Transfering data to user space */
|
||||
copy_to_user(buf,memory_buffer,1);
|
||||
|
||||
/* Changing reading position as best suits */
|
||||
if (*f_pos == 0) {
|
||||
*f_pos+=1;
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
ssize_t memory_write( struct file *filp, char *buf,
|
||||
size_t count, loff_t *f_pos) {
|
||||
|
||||
char *tmp;
|
||||
|
||||
tmp=buf+count-1;
|
||||
copy_from_user(memory_buffer,tmp,1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-jz4740/gpio.h>
|
||||
|
||||
#define FPGA_IRQ_PIN JZ_GPIO_PORTC(15)
|
||||
#define FPGA_CS JZ_GPIO_PORTB(26)
|
||||
#define FPGA_BASE_BEGIN 0x15000000
|
||||
#define FPGA_BASE_END 0x17FFFFFF
|
||||
|
||||
static unsigned int key_p;
|
||||
static unsigned int key_e;
|
||||
|
||||
/*
|
||||
* Scancode to keycode tables. These are just the default setting, and
|
||||
* are loadable via a userland utility.
|
||||
*/
|
||||
|
||||
#define ATKBD_KEYMAP_SIZE 512
|
||||
|
||||
static const unsigned short atkbd_set2_keycode[ATKBD_KEYMAP_SIZE] = {
|
||||
|
||||
#ifdef CONFIG_KEYBOARD_ATKBD_HP_KEYCODES
|
||||
//stream mode
|
||||
iowrite32(0x000000EA,ioaddress);
|
||||
mb();
|
||||
/* XXX: need a more general approach */
|
||||
|
||||
#include "hpps2atkbd.h" /* include the keyboard scancodes */
|
||||
|
||||
#else
|
||||
0, 67, 65, 63, 61, 59, 60, 88, 0, 68, 66, 64, 62, 15, 41,117,
|
||||
0, 56, 42, 93, 29, 16, 2, 0, 0, 0, 44, 31, 30, 17, 3, 0,
|
||||
0, 46, 45, 32, 18, 5, 4, 95, 0, 57, 47, 33, 20, 19, 6,183,
|
||||
0, 49, 48, 35, 34, 21, 7,184, 0, 0, 50, 36, 22, 8, 9,185,
|
||||
0, 51, 37, 23, 24, 11, 10, 0, 0, 52, 53, 38, 39, 25, 12, 0,
|
||||
0, 89, 40, 0, 26, 13, 0, 0, 58, 54, 28, 27, 0, 43, 0, 85,
|
||||
0, 86, 91, 90, 92, 0, 14, 94, 0, 79,124, 75, 71,121, 0, 0,
|
||||
82, 83, 80, 76, 77, 72, 1, 69, 87, 78, 81, 74, 55, 73, 70, 99,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
217,100,255, 0, 97,165, 0, 0,156, 0, 0, 0, 0, 0, 0,125,
|
||||
173,114, 0,113, 0, 0, 0,126,128, 0, 0,140, 0, 0, 0,127,
|
||||
159, 0,115, 0,164, 0, 0,116,158, 0,172,166, 0, 0, 0,142,
|
||||
157, 0, 0, 0, 0, 0, 0, 0,155, 0, 98, 0, 0,163, 0, 0,
|
||||
226, 0, 0, 0, 0, 0, 0, 0, 0,255, 96, 0, 0, 0,143, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0,107, 0,105,102, 0, 0,112,
|
||||
110,111,108,112,106,103, 0,119, 0,118,109, 0, 99,104,119, 0,
|
||||
|
||||
0, 0, 0, 65, 99,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct input_dev *ps2kbd_dev;
|
||||
static void __iomem *ioaddress;
|
||||
|
||||
static irqreturn_t ps2_keyboard_interrupt(int irq, void *id)
|
||||
{
|
||||
unsigned char scancode, keycode;
|
||||
|
||||
scancode = (unsigned char)(ioread32(ioaddress)& 0XFF);
|
||||
rmb();
|
||||
|
||||
//printk(KERN_INFO "scancode %x\n", scancode);
|
||||
|
||||
if (scancode == 0xAA)printk(KERN_INFO "PS/2 keyboard. ok\n");
|
||||
else if (scancode == 0xFC)printk(KERN_INFO "PS/2 keyboard. error\n");
|
||||
else if (scancode == 0xF0)key_p=0;
|
||||
else if (scancode == 0xE0)key_e=1;
|
||||
else if (scancode <= 0x7E){ /* scancodes < 0xf2 are keys */
|
||||
|
||||
keycode = atkbd_set2_keycode[scancode+0x80*key_e];
|
||||
|
||||
input_report_key(ps2kbd_dev, keycode, key_p);
|
||||
input_sync(ps2kbd_dev);
|
||||
key_p=1;
|
||||
key_e=0;
|
||||
} else /* scancodes >= 0xf2 are mouse data, most likely */
|
||||
printk(KERN_INFO "ps2kbd: unhandled scancode %x\n", scancode);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __init ps2_keyboard_init(void)
|
||||
{
|
||||
|
||||
int i, error, res, irq;
|
||||
|
||||
key_p=1;
|
||||
key_e=0;
|
||||
|
||||
ps2kbd_dev = input_allocate_device();
|
||||
if (!ps2kbd_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
ps2kbd_dev->name = "PS2 Keyboard";
|
||||
ps2kbd_dev->phys = "ps2kbd/input0";
|
||||
ps2kbd_dev->id.bustype = BUS_HOST;
|
||||
ps2kbd_dev->id.vendor = 0x0001;
|
||||
ps2kbd_dev->id.product = 0x0001;
|
||||
ps2kbd_dev->id.version = 0x0100;
|
||||
|
||||
ps2kbd_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
|
||||
ps2kbd_dev->keycode = atkbd_set2_keycode;
|
||||
ps2kbd_dev->keycodesize = sizeof(unsigned short);
|
||||
ps2kbd_dev->keycodemax = ARRAY_SIZE(atkbd_set2_keycode);
|
||||
|
||||
for (i = 0; i < ATKBD_KEYMAP_SIZE; i++) {
|
||||
set_bit(atkbd_set2_keycode[i], ps2kbd_dev->keybit);
|
||||
}
|
||||
|
||||
/* error check */
|
||||
error = input_register_device(ps2kbd_dev);
|
||||
if (error) {
|
||||
input_free_device(ps2kbd_dev);
|
||||
return error;
|
||||
}
|
||||
|
||||
/* Set up the FGPA irq line */
|
||||
irq = gpio_to_irq(FPGA_IRQ_PIN);
|
||||
res = request_irq(irq, ps2_keyboard_interrupt, IRQF_DISABLED | IRQF_TRIGGER_RISING, "FPGA - IRQ", NULL); // IRQF_TRIGGER_FALLING
|
||||
|
||||
/* Set GPIOB26 as part of External Memory Controller*/
|
||||
jz_gpio_set_function (FPGA_CS, JZ_GPIO_FUNC_NONE);
|
||||
/* Use ioremap to get a handle on our region */
|
||||
ioaddress = __ioremap(FPGA_BASE_BEGIN, FPGA_BASE_END - FPGA_BASE_BEGIN, _CACHE_UNCACHED);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit ps2_keyboard_exit(void)
|
||||
{
|
||||
free_irq(FPGA_IRQ_PIN, NULL);
|
||||
__iounmap(ioaddress);
|
||||
input_unregister_device(ps2kbd_dev);
|
||||
}
|
||||
|
||||
module_init(ps2_keyboard_init);
|
||||
module_exit(ps2_keyboard_exit);
|
||||
|
||||
MODULE_AUTHOR("Ari Bejarano <aabejaranoh@unal.edu.co>");
|
||||
MODULE_DESCRIPTION("PS/2 Keyboard Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:ps2-keyboard");
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 23 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 8.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 10 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 46 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 49 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 38 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 56 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 12 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 12 KiB |
|
|
@ -0,0 +1,45 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12:22:40 10/07/2010
|
||||
// Design Name:
|
||||
// Module Name: kb_ps2
|
||||
// Project Name: keyboard
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description: controlador de teclado
|
||||
//
|
||||
// Dependencies: ps2_rx, ps2_tx
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module kb_ps2(
|
||||
input wire clk, reset,
|
||||
input wire we_ps2,
|
||||
inout wire ps2_data, ps2_clk,
|
||||
input wire [7:0] din,
|
||||
output wire rx_done, tx_done,
|
||||
output wire [7:0] dout
|
||||
);
|
||||
|
||||
// signal declaration
|
||||
wire tx_idle;
|
||||
|
||||
// instantiate ps2 receiver
|
||||
ps2_rx ps2_rx_1
|
||||
(.clk(clk), .reset(reset), .rx_en(tx_idle),
|
||||
.ps2_data(ps2_data), .ps2_clk(ps2_clk),
|
||||
.rx_done(rx_done), .dout(dout));
|
||||
// instantiate ps2 transmitter
|
||||
ps2_tx ps2_tx_1
|
||||
(.clk(clk), .reset(reset), .we_ps2(we_ps2),
|
||||
.din(din), .ps2_data(ps2_data), .ps2_clk(ps2_clk),
|
||||
.tx_idle(tx_idle), .tx_done(tx_done));
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
NET clk LOC = "P38";
|
||||
NET reset LOC = "P30";
|
||||
NET led LOC = "P44";
|
||||
NET irq_kb LOC = "P71";
|
||||
|
||||
#ADDRESS BUS
|
||||
NET "addr<12>" LOC = "P90";
|
||||
NET "addr<11>" LOC = "P91";
|
||||
NET "addr<10>" LOC = "P85";
|
||||
NET "addr<9>" LOC = "P92";
|
||||
NET "addr<8>" LOC = "P94";
|
||||
NET "addr<7>" LOC = "P95";
|
||||
NET "addr<6>" LOC = "P98";
|
||||
NET "addr<5>" LOC = "P3";
|
||||
NET "addr<4>" LOC = "P2";
|
||||
NET "addr<3>" LOC = "P78";
|
||||
NET "addr<2>" LOC = "P79";
|
||||
NET "addr<1>" LOC = "P83";
|
||||
NET "addr<0>" LOC = "P84";
|
||||
|
||||
#DATA BUS
|
||||
NET "data<7>" LOC = "P4";
|
||||
NET "data<6>" LOC = "P5";
|
||||
NET "data<5>" LOC = "P9";
|
||||
NET "data<4>" LOC = "P10";
|
||||
NET "data<3>" LOC = "P11";
|
||||
NET "data<2>" LOC = "P12";
|
||||
NET "data<1>" LOC = "P15";
|
||||
NET "data<0>" LOC = "P16";
|
||||
|
||||
#CONTROL BUS
|
||||
NET "nwe" LOC = "P88";
|
||||
NET "noe" LOC = "P86";
|
||||
NET "ncs" LOC = "P69";
|
||||
|
||||
#PS/2
|
||||
NET ps2_data LOC = "P65";#"P68";
|
||||
NET ps2_clk LOC = "P62";#"P63";
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: UNAL
|
||||
// Engineer: Ari Bejarano
|
||||
//
|
||||
// Create Date: 16:28:50 09/30/2010
|
||||
// Design Name: ps2_interface
|
||||
// Module Name: ps2_interface
|
||||
// Project Name: ps2_interface
|
||||
// Target Devices:
|
||||
// Tool versions: 2.0
|
||||
// Description: ¬¬
|
||||
//
|
||||
// Dependencies: sync.v, writePulseGenerator.v, kb_ps2
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module ps2_interface(clk, data, addr, nwe, ncs, noe, reset, ps2_data, ps2_clk, irq_kb, led);
|
||||
|
||||
parameter N = 13, M = 8;// M # de lineas de datos, N # de lineas de dirección
|
||||
|
||||
input clk, nwe, ncs, noe, reset;
|
||||
input [N-1:0] addr;
|
||||
inout [M-1:0] data;
|
||||
inout ps2_clk;
|
||||
inout ps2_data;
|
||||
output irq_kb;
|
||||
output led;
|
||||
|
||||
wire sncs;
|
||||
wire snwe;
|
||||
wire [N-1:0] buffer_addr;
|
||||
wire [M-1:0] rdBus;
|
||||
wire [M-1:0] wdBus;
|
||||
wire we;
|
||||
wire rx_done;
|
||||
|
||||
assign led = ps2_clk;
|
||||
|
||||
sync # (.N(13), .M(8))// M # de lineas de datos, N # de lineas de dirección
|
||||
sync_U1(.clk(clk),
|
||||
.data(data),
|
||||
.addr(addr),
|
||||
.nwe(nwe),
|
||||
.ncs(ncs),
|
||||
.noe(noe),
|
||||
.rdBus(rdBus),
|
||||
.sncs(sncs),
|
||||
.snwe(snwe),
|
||||
.buffer_addr(buffer_addr),
|
||||
.buffer_data(wdBus));
|
||||
|
||||
writePulseGenerator writePulseGenerator_U2 (.clk(clk),
|
||||
.snwe(snwe),
|
||||
.sncs(sncs),
|
||||
.reset(reset),
|
||||
.we(we));
|
||||
|
||||
kb_ps2 kb_ps2_U3(.clk(~clk),
|
||||
.reset(~reset),
|
||||
.we_ps2(we),
|
||||
.ps2_data(ps2_data),
|
||||
.ps2_clk(ps2_clk),
|
||||
.din(wdBus),
|
||||
.rx_done(rx_done),
|
||||
.tx_done(),
|
||||
.dout(rdBus));
|
||||
|
||||
pulse_expander pulse_expander_U4(
|
||||
.clk(clk),
|
||||
.reset(~reset),
|
||||
.pulse_in(rx_done),
|
||||
.pulse_out(irq_kb)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
iverilog -o ps2_interface_TF ps2_interface_TF.v ps2_interface.v kb_ps2.v ps2_rx.v ps2_tx.v pulse_expander.v sync.v writePulseGenerator.v
|
||||
vvp ps2_interface_TF
|
||||
gtkwave ps2_interface_TF.vcd
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 10:48:20 10/15/2010
|
||||
// Design Name: ps2_interface
|
||||
// Module Name: /home/ari/Xilinx_Projects/ps2_interface/ps2_interface_TF.v
|
||||
// Project Name: ps2_interface
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: ps2_interface
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ps2_interface_TF;
|
||||
|
||||
// Inputs
|
||||
reg clk;
|
||||
reg [12:0] addr;
|
||||
reg nwe;
|
||||
reg ncs;
|
||||
reg noe;
|
||||
reg reset;
|
||||
|
||||
// Outputs
|
||||
wire irq_kb;
|
||||
wire led;
|
||||
|
||||
// Bidirs
|
||||
wire [7:0] data;
|
||||
wire ps2_data;
|
||||
wire ps2_clk;
|
||||
|
||||
reg ps2_datar;
|
||||
reg ps2_clkr;
|
||||
reg [7:0] datar;
|
||||
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
ps2_interface uut (
|
||||
.clk(clk),
|
||||
.data(data),
|
||||
.addr(addr),
|
||||
.nwe(nwe),
|
||||
.ncs(ncs),
|
||||
.noe(noe),
|
||||
.reset(reset),
|
||||
.ps2_data(ps2_data),
|
||||
.ps2_clk(ps2_clk),
|
||||
.irq_kb(irq_kb),
|
||||
.led(led)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
clk = 0;
|
||||
addr = 0;
|
||||
nwe = 1;
|
||||
ncs = 0;
|
||||
noe = 1;
|
||||
reset = 1;
|
||||
ps2_datar = 1;
|
||||
ps2_clkr = 1;
|
||||
datar = 8'bz;
|
||||
|
||||
// Wait 100 ns for global reset to finish
|
||||
#100;
|
||||
|
||||
// Add stimulus here
|
||||
reset = 0;
|
||||
#100;
|
||||
reset = 1;
|
||||
#100;
|
||||
|
||||
//start
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data1
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data2
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data3
|
||||
#25000;
|
||||
ps2_datar=1;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data4
|
||||
#25000;
|
||||
ps2_datar=1;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data5
|
||||
#25000;
|
||||
ps2_datar=1;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data6
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data7
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//data8
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//parity
|
||||
#25000;
|
||||
ps2_datar=0;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
//stop
|
||||
#25000;
|
||||
ps2_datar=1;
|
||||
#25000;
|
||||
ps2_clkr=0;
|
||||
#50000;
|
||||
ps2_clkr=1;
|
||||
|
||||
#50000;
|
||||
datar=8'b01011010;
|
||||
noe = 0;
|
||||
nwe = 0;
|
||||
ps2_datar=1'bz;
|
||||
ps2_clkr=1'bz;
|
||||
|
||||
#400
|
||||
nwe = 1;
|
||||
|
||||
#80000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
#50000
|
||||
ps2_clkr=0;
|
||||
#50000
|
||||
ps2_clkr=1;
|
||||
|
||||
end
|
||||
|
||||
always
|
||||
#10 clk=!clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile ("ps2_interface_TF.vcd");
|
||||
$dumpvars;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$display("\t\ttime,\tclk,\tdata,\taddr,\tnwe,\tncs,\tnoe,\treset,\tps2_data,\tps2_clk,\tirq_kb");
|
||||
$monitor("%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d",
|
||||
$time,clk,data,addr,nwe,ncs,noe,reset,ps2_data,ps2_clk,irq_kb);
|
||||
end
|
||||
|
||||
initial
|
||||
#3000000 $finish;
|
||||
|
||||
assign ps2_clk=ps2_clkr;
|
||||
assign ps2_data=ps2_datar;
|
||||
assign data=datar;
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,98 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module ps2_rx(
|
||||
input wire clk, reset,
|
||||
input wire ps2_data, ps2_clk, rx_en,
|
||||
output reg rx_done,
|
||||
output wire [7:0] dout
|
||||
);
|
||||
|
||||
//signal declaration
|
||||
reg [1:0] state_reg, state_next;
|
||||
reg [7:0] filter_reg;
|
||||
wire [7:0] filter_next;
|
||||
reg f_ps2c_reg;
|
||||
wire f_ps2c_next;
|
||||
reg [3:0] n_reg, n_next;
|
||||
reg [10:0] b_reg, b_next;
|
||||
wire fall_edge;
|
||||
|
||||
//====================================================
|
||||
// falling - edge generation for ps2_clk
|
||||
//====================================================
|
||||
always @(posedge clk, posedge reset)
|
||||
if (reset)
|
||||
begin
|
||||
filter_reg <= 0;
|
||||
f_ps2c_reg <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
filter_reg <= filter_next;
|
||||
f_ps2c_reg <= f_ps2c_next;
|
||||
end
|
||||
|
||||
assign filter_next = {ps2_clk, filter_reg[7:1]};
|
||||
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
|
||||
(filter_reg==8'b00000000) ? 1'b0 :
|
||||
f_ps2c_reg;
|
||||
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
|
||||
|
||||
//==============================================================
|
||||
// FSM
|
||||
//==============================================================
|
||||
// state & data registers
|
||||
always @(posedge clk, posedge reset)
|
||||
if(reset)
|
||||
begin
|
||||
state_reg <= 1;
|
||||
n_reg <= 0;
|
||||
b_reg <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state_reg <= state_next;
|
||||
n_reg <= n_next;
|
||||
b_reg <= b_next;
|
||||
end
|
||||
// next state logic
|
||||
always @(*)
|
||||
begin
|
||||
state_next = state_reg;
|
||||
n_next = n_reg;
|
||||
b_next = b_reg;
|
||||
rx_done = 1'b0;
|
||||
case(state_reg)
|
||||
1:
|
||||
if(fall_edge & rx_en)
|
||||
begin
|
||||
//shift in start bit
|
||||
b_next = {ps2_data, b_reg[10:1]};
|
||||
n_next = 4'b1001;
|
||||
state_next = 2;
|
||||
end
|
||||
2: // 8 data + 1 parity + 1 stop
|
||||
begin
|
||||
if(fall_edge)
|
||||
begin
|
||||
b_next = {ps2_data, b_reg[10:1]};
|
||||
|
||||
if(n_reg==0)
|
||||
state_next = 3;
|
||||
else
|
||||
n_next = n_reg-1;
|
||||
end
|
||||
end
|
||||
3: // 1 extra clock to complete the last shift
|
||||
begin
|
||||
state_next = 1;
|
||||
rx_done = 1'b1;
|
||||
end
|
||||
default: state_next = 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
//output
|
||||
assign dout = b_reg[8:1]; //data bits
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11:52:20 10/07/2010
|
||||
// Design Name:
|
||||
// Module Name: ps2_tx
|
||||
// Project Name: keyboard
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description: transmisor de teclado ps2
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ps2_tx
|
||||
(
|
||||
input wire clk, reset,
|
||||
input wire we_ps2,
|
||||
input wire [7:0] din,
|
||||
inout wire ps2_data, ps2_clk,
|
||||
output reg tx_idle, tx_done
|
||||
);
|
||||
|
||||
// symbolic state declaration
|
||||
localparam [2:0]
|
||||
idle = 3'b000,
|
||||
rts = 3'b001,
|
||||
start = 3'b010,
|
||||
data = 3'b011,
|
||||
stop = 3'b100;
|
||||
|
||||
// signal declaration
|
||||
reg [2:0] state_reg, state_next;
|
||||
reg [7:0] filter_reg;
|
||||
wire [7:0] filter_next;
|
||||
reg f_ps2c_reg;
|
||||
wire f_ps2c_next;
|
||||
reg [3:0] n_reg, n_next;
|
||||
reg [8:0] b_reg, b_next;
|
||||
reg [12:0] c_reg, c_next;
|
||||
wire par, fall_edge;
|
||||
reg ps2c_out, ps2d_out;
|
||||
reg tri_c, tri_d;
|
||||
|
||||
|
||||
//=================================================
|
||||
// falling-edge generation for ps2_clk
|
||||
//=================================================
|
||||
always @(posedge clk, posedge reset)
|
||||
if (reset)
|
||||
begin
|
||||
filter_reg <= 0;
|
||||
f_ps2c_reg <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
filter_reg <= filter_next;
|
||||
f_ps2c_reg <= f_ps2c_next;
|
||||
end
|
||||
|
||||
assign filter_next = {ps2_clk, filter_reg[7:1]};
|
||||
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
|
||||
(filter_reg==8'b00000000) ? 1'b0 :
|
||||
f_ps2c_reg;
|
||||
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
|
||||
|
||||
//=================================================
|
||||
// FSM
|
||||
//=================================================
|
||||
// state & data registers
|
||||
always @(posedge clk, posedge reset)
|
||||
if (reset)
|
||||
begin
|
||||
state_reg <= idle;
|
||||
c_reg <= 0;
|
||||
n_reg <= 0;
|
||||
b_reg <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state_reg <= state_next;
|
||||
c_reg <= c_next;
|
||||
n_reg <= n_next;
|
||||
b_reg <= b_next;
|
||||
end
|
||||
|
||||
// odd parity bit
|
||||
assign par = ~(^din);
|
||||
|
||||
// FSM next-state logic
|
||||
always @*
|
||||
begin
|
||||
state_next = state_reg;
|
||||
c_next = c_reg;
|
||||
n_next = n_reg;
|
||||
b_next = b_reg;
|
||||
tx_done = 1'b0;
|
||||
ps2c_out = 1'bz;
|
||||
ps2d_out = 1'bz;
|
||||
tri_c = 1'b0;
|
||||
tri_d = 1'b0;
|
||||
tx_idle = 1'b0;
|
||||
case (state_reg)
|
||||
idle:
|
||||
begin
|
||||
tx_idle = 1'b1;
|
||||
if (we_ps2)
|
||||
begin
|
||||
b_next = {par, din};
|
||||
c_next = 13'h1fff; // 2^13-1
|
||||
state_next = rts;
|
||||
end
|
||||
end
|
||||
rts: // request to send
|
||||
begin
|
||||
ps2c_out = 1'b0;
|
||||
tri_c = 1'b1;
|
||||
c_next = c_reg - 1;
|
||||
if (c_reg==0)
|
||||
state_next = start;
|
||||
end
|
||||
start: // assert start bit
|
||||
begin
|
||||
ps2d_out = 1'b0;
|
||||
tri_d = 1'b1;
|
||||
if (fall_edge)
|
||||
begin
|
||||
n_next = 4'h8;
|
||||
state_next = data;
|
||||
end
|
||||
end
|
||||
data: // 8 data + 1 parity
|
||||
begin
|
||||
ps2d_out = (b_reg[0])? 1'bz : 1'b0;
|
||||
tri_d = 1'b1;
|
||||
if (fall_edge)
|
||||
begin
|
||||
b_next = {1'b0, b_reg[8:1]};
|
||||
if (n_reg == 0)
|
||||
state_next = stop;
|
||||
else
|
||||
n_next = n_reg - 1;
|
||||
end
|
||||
end
|
||||
stop: // assume floating high for ps2_data
|
||||
if (fall_edge)
|
||||
begin
|
||||
state_next = idle;
|
||||
tx_done = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// tri-state buffers
|
||||
assign ps2_clk = (tri_c) ? ps2c_out : 1'bz;
|
||||
assign ps2_data = (tri_d) ? ps2d_out : 1'bz;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: U.N
|
||||
// Engineer: Ari Andrés Bejarano H.
|
||||
//
|
||||
// Create Date: 07:19:56 10/15/2010
|
||||
// Design Name:
|
||||
// Module Name: pulse_expander
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description: expande pulse_out = (pulse_in) + (num * pulses of clk)
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module pulse_expander(
|
||||
input clk,
|
||||
input reset,
|
||||
input pulse_in,
|
||||
output reg pulse_out
|
||||
);
|
||||
|
||||
parameter num = 5000;
|
||||
|
||||
reg [24:0] cnt;
|
||||
reg flag;
|
||||
|
||||
always@(posedge clk)begin
|
||||
|
||||
if(reset)
|
||||
begin
|
||||
cnt <= 0;
|
||||
pulse_out <= 0;
|
||||
flag <= 0;
|
||||
end
|
||||
else
|
||||
if(pulse_in || flag)
|
||||
if(cnt < num)
|
||||
begin
|
||||
cnt <= cnt+1;
|
||||
pulse_out <= 1;
|
||||
flag <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt <= 0;
|
||||
pulse_out <= 0;
|
||||
flag <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 08:01:22 10/15/2010
|
||||
// Design Name: pulse_expander
|
||||
// Module Name: /home/ari/Xilinx_Projects/keyboard/pulse_expander_TF.v
|
||||
// Project Name: keyboard
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: pulse_expander
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module pulse_expander_TF;
|
||||
|
||||
// Inputs
|
||||
reg clk;
|
||||
reg reset;
|
||||
reg pulse_in;
|
||||
|
||||
// Outputs
|
||||
wire pulse_out;
|
||||
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
pulse_expander uut (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.pulse_in(pulse_in),
|
||||
.pulse_out(pulse_out)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
clk = 0;
|
||||
reset = 0;
|
||||
pulse_in = 0;
|
||||
|
||||
// Wait 100 ns for global reset to finish
|
||||
#100;
|
||||
// Add stimulus here
|
||||
reset = 1;
|
||||
#100;
|
||||
reset = 0;
|
||||
#100;
|
||||
pulse_in = 1;
|
||||
#20;
|
||||
pulse_in = 0;
|
||||
#400;
|
||||
pulse_in = 1;
|
||||
#20;
|
||||
pulse_in = 0;
|
||||
end
|
||||
|
||||
always
|
||||
#10 clk=!clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile ("pulse_expander_TF.vcd");
|
||||
$dumpvars;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$display("\t\ttime,\tclk,\treset,\tpulse_in,\tpulse_out");
|
||||
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,pulse_in,pulse_out);
|
||||
end
|
||||
|
||||
initial
|
||||
#2000 $finish;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module sync # (parameter N = 13, M = 8)
|
||||
(input clk,
|
||||
inout [M-1:0] data,
|
||||
input [N-1:0] addr,
|
||||
input nwe,
|
||||
input ncs,
|
||||
input noe,
|
||||
input [M-1:0] rdBus,
|
||||
output reg sncs,
|
||||
output reg snwe,
|
||||
output reg [N-1:0] buffer_addr,
|
||||
output [M-1:0] buffer_data);
|
||||
|
||||
|
||||
// interefaz signals assignments
|
||||
wire T = ~noe | ncs;
|
||||
assign data = T?8'bZ:rdBus;
|
||||
assign buffer_data = data;
|
||||
|
||||
// synchronize assignment
|
||||
always @(negedge clk)
|
||||
begin
|
||||
sncs <= ncs;
|
||||
snwe <= nwe;
|
||||
buffer_addr <= addr;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module writePulseGenerator (input clk,
|
||||
input snwe,
|
||||
input sncs,
|
||||
input reset,
|
||||
output reg we);
|
||||
|
||||
reg w_st;
|
||||
|
||||
// write access cpu to bram
|
||||
always @(posedge clk)
|
||||
if(~reset) {w_st, we} <= 0;
|
||||
else begin
|
||||
|
||||
case (w_st)
|
||||
0: begin
|
||||
we <= 0;
|
||||
if(sncs | snwe)
|
||||
w_st <= 1;
|
||||
end
|
||||
1: begin
|
||||
if(~(sncs | snwe))
|
||||
begin
|
||||
we <= 1;
|
||||
w_st <= 0;
|
||||
end
|
||||
else we <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
#############################################################################
|
||||
# Makefile for building: TexEditor
|
||||
# Generated by qmake (2.01a) (Qt 4.7.0) on: sáb nov 27 09:53:47 2010
|
||||
# Project: TexEditor.pro
|
||||
# Template: app
|
||||
# Command: /home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/qmake -spec ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/qws/linux-openwrt-g++ -o Makefile TexEditor.pro
|
||||
#############################################################################
|
||||
|
||||
####### Compiler, tools and options
|
||||
|
||||
CC = /home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/mipsel-openwrt-linux-uclibc-gcc
|
||||
CXX = /home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/mipsel-openwrt-linux-uclibc-g++
|
||||
DEFINES = -DQT_NO_DEBUG -DQT_GUI_LIB -DQT_NETWORK_LIB -DQT_CORE_LIB -DQT_SHARED
|
||||
CFLAGS = -Os -pipe -mips32 -mtune=mips32 -funit-at-a-time -fhonour-copts -msoft-float -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/include/freetype2 -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/include -O2 -Wall -W -D_REENTRANT $(DEFINES)
|
||||
CXXFLAGS = -Os -pipe -mips32 -mtune=mips32 -funit-at-a-time -fhonour-copts -msoft-float -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/include/freetype2 -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/include -I/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/include -O2 -Wall -W -D_REENTRANT $(DEFINES)
|
||||
INCPATH = -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/qws/linux-openwrt-g++ -I. -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/include/QtCore -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/include/QtNetwork -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/include/QtGui -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/include -I. -I. -I../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/include
|
||||
LINK = /home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/mipsel-openwrt-linux-uclibc-g++
|
||||
LFLAGS = -L/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/lib -L//home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib -L//home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/lib -Wl,-rpath-link=/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/lib -Wl,-O1
|
||||
LIBS = $(SUBLIBS) -L/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib -lQtGui -L/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/target-mipsel_uClibc-0.9.30.1/usr/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/lib -L/home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/lib -lQtNetwork -lQtCore -lpthread
|
||||
AR = /home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/mipsel-openwrt-linux-uclibc-ar cqs
|
||||
RANLIB = /home/ari/sie/p/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/mipsel-openwrt-linux-uclibc-ranlib
|
||||
QMAKE = /home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/qmake
|
||||
TAR = tar -cf
|
||||
COMPRESS = gzip -9f
|
||||
COPY = cp -f
|
||||
SED = sed
|
||||
COPY_FILE = $(COPY)
|
||||
COPY_DIR = $(COPY) -r
|
||||
STRIP = :
|
||||
INSTALL_FILE = install -m 644 -p
|
||||
INSTALL_DIR = $(COPY_DIR)
|
||||
INSTALL_PROGRAM = install -m 755 -p
|
||||
DEL_FILE = rm -f
|
||||
SYMLINK = ln -f -s
|
||||
DEL_DIR = rmdir
|
||||
MOVE = mv -f
|
||||
CHK_DIR_EXISTS= test -d
|
||||
MKDIR = mkdir -p
|
||||
|
||||
####### Output directory
|
||||
|
||||
OBJECTS_DIR = ./
|
||||
|
||||
####### Files
|
||||
|
||||
SOURCES = main.cpp \
|
||||
mainwindow.cpp moc_mainwindow.cpp \
|
||||
qrc_images.cpp
|
||||
OBJECTS = main.o \
|
||||
mainwindow.o \
|
||||
moc_mainwindow.o \
|
||||
qrc_images.o
|
||||
DIST = ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/g++.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/unix.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/linux.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/qws.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_functions.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_config.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/exclusive_builds.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_pre.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/release.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_post.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/warn_on.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/unix/thread.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/moc.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/resources.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/uic.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/yacc.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/lex.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/include_source_dir.prf \
|
||||
TexEditor.pro
|
||||
QMAKE_TARGET = TexEditor
|
||||
DESTDIR =
|
||||
TARGET = TexEditor
|
||||
|
||||
first: all
|
||||
####### Implicit rules
|
||||
|
||||
.SUFFIXES: .o .c .cpp .cc .cxx .C
|
||||
|
||||
.cpp.o:
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o "$@" "$<"
|
||||
|
||||
.cc.o:
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o "$@" "$<"
|
||||
|
||||
.cxx.o:
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o "$@" "$<"
|
||||
|
||||
.C.o:
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o "$@" "$<"
|
||||
|
||||
.c.o:
|
||||
$(CC) -c $(CFLAGS) $(INCPATH) -o "$@" "$<"
|
||||
|
||||
####### Build rules
|
||||
|
||||
all: Makefile $(TARGET)
|
||||
|
||||
$(TARGET): ui_mainwindow.h $(OBJECTS)
|
||||
$(LINK) $(LFLAGS) -o $(TARGET) $(OBJECTS) $(OBJCOMP) $(LIBS)
|
||||
|
||||
Makefile: TexEditor.pro ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/qws/linux-openwrt-g++/qmake.conf ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/g++.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/unix.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/linux.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/qws.conf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_functions.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_config.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/exclusive_builds.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_pre.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/release.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_post.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/warn_on.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/unix/thread.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/moc.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/resources.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/uic.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/yacc.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/lex.prf \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/include_source_dir.prf \
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtGui.prl \
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtNetwork.prl \
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtCore.prl
|
||||
$(QMAKE) -spec ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/qws/linux-openwrt-g++ -o Makefile TexEditor.pro
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/g++.conf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/unix.conf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/linux.conf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/common/qws.conf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_functions.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt_config.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/exclusive_builds.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_pre.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/release.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/default_post.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/warn_on.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/qt.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/unix/thread.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/moc.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/resources.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/uic.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/yacc.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/lex.prf:
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/features/include_source_dir.prf:
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtGui.prl:
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtNetwork.prl:
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/lib/libQtCore.prl:
|
||||
qmake: FORCE
|
||||
@$(QMAKE) -spec ../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/mkspecs/qws/linux-openwrt-g++ -o Makefile TexEditor.pro
|
||||
|
||||
dist:
|
||||
@$(CHK_DIR_EXISTS) .tmp/TexEditor1.0.0 || $(MKDIR) .tmp/TexEditor1.0.0
|
||||
$(COPY_FILE) --parents $(SOURCES) $(DIST) .tmp/TexEditor1.0.0/ && $(COPY_FILE) --parents mainwindow.h .tmp/TexEditor1.0.0/ && $(COPY_FILE) --parents images.qrc .tmp/TexEditor1.0.0/ && $(COPY_FILE) --parents main.cpp mainwindow.cpp .tmp/TexEditor1.0.0/ && $(COPY_FILE) --parents mainwindow.ui .tmp/TexEditor1.0.0/ && (cd `dirname .tmp/TexEditor1.0.0` && $(TAR) TexEditor1.0.0.tar TexEditor1.0.0 && $(COMPRESS) TexEditor1.0.0.tar) && $(MOVE) `dirname .tmp/TexEditor1.0.0`/TexEditor1.0.0.tar.gz . && $(DEL_FILE) -r .tmp/TexEditor1.0.0
|
||||
|
||||
|
||||
clean:compiler_clean
|
||||
-$(DEL_FILE) $(OBJECTS)
|
||||
-$(DEL_FILE) *~ core *.core
|
||||
|
||||
|
||||
####### Sub-libraries
|
||||
|
||||
distclean: clean
|
||||
-$(DEL_FILE) $(TARGET)
|
||||
-$(DEL_FILE) Makefile
|
||||
|
||||
|
||||
check: first
|
||||
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/moc:
|
||||
(cd $(QTDIR)/src/tools/moc && $(MAKE))
|
||||
|
||||
mocclean: compiler_moc_header_clean compiler_moc_source_clean
|
||||
|
||||
mocables: compiler_moc_header_make_all compiler_moc_source_make_all
|
||||
|
||||
compiler_moc_header_make_all: moc_mainwindow.cpp
|
||||
compiler_moc_header_clean:
|
||||
-$(DEL_FILE) moc_mainwindow.cpp
|
||||
moc_mainwindow.cpp: mainwindow.h \
|
||||
../../../../sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/moc
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/moc $(DEFINES) $(INCPATH) mainwindow.h -o moc_mainwindow.cpp
|
||||
|
||||
compiler_rcc_make_all: qrc_images.cpp
|
||||
compiler_rcc_clean:
|
||||
-$(DEL_FILE) qrc_images.cpp
|
||||
qrc_images.cpp: images.qrc \
|
||||
images/new.png \
|
||||
images/copy.png \
|
||||
images/cut.png \
|
||||
images/save.png \
|
||||
images/paste.png \
|
||||
images/open.png
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/rcc -name images images.qrc -o qrc_images.cpp
|
||||
|
||||
compiler_image_collection_make_all: qmake_image_collection.cpp
|
||||
compiler_image_collection_clean:
|
||||
-$(DEL_FILE) qmake_image_collection.cpp
|
||||
compiler_moc_source_make_all:
|
||||
compiler_moc_source_clean:
|
||||
compiler_uic_make_all: ui_mainwindow.h
|
||||
compiler_uic_clean:
|
||||
-$(DEL_FILE) ui_mainwindow.h
|
||||
ui_mainwindow.h: mainwindow.ui
|
||||
/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0/bin/uic mainwindow.ui -o ui_mainwindow.h
|
||||
|
||||
compiler_yacc_decl_make_all:
|
||||
compiler_yacc_decl_clean:
|
||||
compiler_yacc_impl_make_all:
|
||||
compiler_yacc_impl_clean:
|
||||
compiler_lex_make_all:
|
||||
compiler_lex_clean:
|
||||
compiler_clean: compiler_moc_header_clean compiler_rcc_clean compiler_uic_clean
|
||||
|
||||
####### Compile
|
||||
|
||||
main.o: main.cpp mainwindow.h
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o main.o main.cpp
|
||||
|
||||
mainwindow.o: mainwindow.cpp mainwindow.h \
|
||||
ui_mainwindow.h
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o mainwindow.o mainwindow.cpp
|
||||
|
||||
moc_mainwindow.o: moc_mainwindow.cpp
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o moc_mainwindow.o moc_mainwindow.cpp
|
||||
|
||||
qrc_images.o: qrc_images.cpp
|
||||
$(CXX) -c $(CXXFLAGS) $(INCPATH) -o qrc_images.o qrc_images.cpp
|
||||
|
||||
####### Install
|
||||
|
||||
install: FORCE
|
||||
|
||||
uninstall: FORCE
|
||||
|
||||
FORCE:
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,21 @@
|
|||
#-------------------------------------------------
|
||||
#
|
||||
# Project created by QtCreator 2010-11-20T20:42:53
|
||||
#
|
||||
#-------------------------------------------------
|
||||
|
||||
QT += core gui
|
||||
|
||||
TARGET = TexEditor
|
||||
TEMPLATE = app
|
||||
|
||||
|
||||
SOURCES += main.cpp\
|
||||
mainwindow.cpp
|
||||
|
||||
HEADERS += mainwindow.h
|
||||
|
||||
FORMS += mainwindow.ui
|
||||
|
||||
RESOURCES += \
|
||||
images.qrc
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
<!DOCTYPE QtCreatorProject>
|
||||
<qtcreator>
|
||||
<data>
|
||||
<variable>ProjectExplorer.Project.ActiveTarget</variable>
|
||||
<value type="int">0</value>
|
||||
</data>
|
||||
<data>
|
||||
<variable>ProjectExplorer.Project.EditorSettings</variable>
|
||||
<valuemap type="QVariantMap">
|
||||
<value key="EditorConfiguration.Codec" type="QByteArray">UTF-8</value>
|
||||
</valuemap>
|
||||
</data>
|
||||
<data>
|
||||
<variable>ProjectExplorer.Project.Target.0</variable>
|
||||
<valuemap type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Desktop</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.Target.DesktopTarget</value>
|
||||
<value key="ProjectExplorer.Target.ActiveBuildConfiguration" type="int">0</value>
|
||||
<value key="ProjectExplorer.Target.ActiveRunConfiguration" type="int">0</value>
|
||||
<valuemap key="ProjectExplorer.Target.BuildConfiguration.0" type="QVariantMap">
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.BuildStep.0" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">qmake</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">QtProjectManager.QMakeBuildStep</value>
|
||||
<valuelist key="QtProjectManager.QMakeBuildStep.QMakeArguments" type="QVariantList"/>
|
||||
</valuemap>
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.BuildStep.1" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Make</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.MakeStep</value>
|
||||
<value key="Qt4ProjectManager.MakeStep.Clean" type="bool">false</value>
|
||||
<valuelist key="Qt4ProjectManager.MakeStep.MakeArguments" type="QVariantList"/>
|
||||
<value key="Qt4ProjectManager.MakeStep.MakeCommand" type="QString"></value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.BuildConfiguration.BuildStepsCount" type="int">2</value>
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.CleanStep.0" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Make</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.MakeStep</value>
|
||||
<value key="Qt4ProjectManager.MakeStep.Clean" type="bool">true</value>
|
||||
<valuelist key="Qt4ProjectManager.MakeStep.MakeArguments" type="QVariantList">
|
||||
<value type="QString">clean</value>
|
||||
</valuelist>
|
||||
<value key="Qt4ProjectManager.MakeStep.MakeCommand" type="QString"></value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.BuildConfiguration.CleanStepsCount" type="int">1</value>
|
||||
<value key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment" type="bool">false</value>
|
||||
<valuelist key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges" type="QVariantList"/>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Debug</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.Qt4BuildConfiguration</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.BuildConfiguration" type="int">2</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.BuildDirectory" type="QString">/home/ari/keyboard/src/TexEditor/TexEditor-build-desktop</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.QtVersionId" type="int">2</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.ToolChain" type="int">0</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.UseShadowBuild" type="bool">true</value>
|
||||
</valuemap>
|
||||
<valuemap key="ProjectExplorer.Target.BuildConfiguration.1" type="QVariantMap">
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.BuildStep.0" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">qmake</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">QtProjectManager.QMakeBuildStep</value>
|
||||
<valuelist key="QtProjectManager.QMakeBuildStep.QMakeArguments" type="QVariantList"/>
|
||||
</valuemap>
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.BuildStep.1" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Make</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.MakeStep</value>
|
||||
<value key="Qt4ProjectManager.MakeStep.Clean" type="bool">false</value>
|
||||
<valuelist key="Qt4ProjectManager.MakeStep.MakeArguments" type="QVariantList"/>
|
||||
<value key="Qt4ProjectManager.MakeStep.MakeCommand" type="QString"></value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.BuildConfiguration.BuildStepsCount" type="int">2</value>
|
||||
<valuemap key="ProjectExplorer.BuildConfiguration.CleanStep.0" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Make</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.MakeStep</value>
|
||||
<value key="Qt4ProjectManager.MakeStep.Clean" type="bool">true</value>
|
||||
<valuelist key="Qt4ProjectManager.MakeStep.MakeArguments" type="QVariantList">
|
||||
<value type="QString">clean</value>
|
||||
</valuelist>
|
||||
<value key="Qt4ProjectManager.MakeStep.MakeCommand" type="QString"></value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.BuildConfiguration.CleanStepsCount" type="int">1</value>
|
||||
<value key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment" type="bool">false</value>
|
||||
<valuelist key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges" type="QVariantList"/>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">Release</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.Qt4BuildConfiguration</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.BuildConfiguration" type="int">0</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.BuildDirectory" type="QString">/home/ari/keyboard/src/TexEditor/TexEditor-build-desktop</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.QtVersionId" type="int">2</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.ToolChain" type="int">0</value>
|
||||
<value key="Qt4ProjectManager.Qt4BuildConfiguration.UseShadowBuild" type="bool">true</value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.Target.BuildConfigurationCount" type="int">2</value>
|
||||
<valuemap key="ProjectExplorer.Target.RunConfiguration.0" type="QVariantMap">
|
||||
<value key="ProjectExplorer.ProjectConfiguration.DisplayName" type="QString">TexEditor</value>
|
||||
<value key="ProjectExplorer.ProjectConfiguration.Id" type="QString">Qt4ProjectManager.Qt4RunConfiguration</value>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.BaseEnvironmentBase" type="int">2</value>
|
||||
<valuelist key="Qt4ProjectManager.Qt4RunConfiguration.CommandLineArguments" type="QVariantList"/>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.ProFile" type="QString">TexEditor.pro</value>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.UseDyldImageSuffix" type="bool">false</value>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.UseTerminal" type="bool">false</value>
|
||||
<valuelist key="Qt4ProjectManager.Qt4RunConfiguration.UserEnvironmentChanges" type="QVariantList"/>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.UserSetName" type="bool">false</value>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.UserSetWorkingDirectory" type="bool">false</value>
|
||||
<value key="Qt4ProjectManager.Qt4RunConfiguration.UserWorkingDirectory" type="QString"></value>
|
||||
</valuemap>
|
||||
<value key="ProjectExplorer.Target.RunConfigurationCount" type="int">1</value>
|
||||
</valuemap>
|
||||
</data>
|
||||
<data>
|
||||
<variable>ProjectExplorer.Project.TargetCount</variable>
|
||||
<value type="int">1</value>
|
||||
</data>
|
||||
<data>
|
||||
<variable>ProjectExplorer.Project.Updater.FileVersion</variable>
|
||||
<value type="int">4</value>
|
||||
</data>
|
||||
</qtcreator>
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#!/bin/sh
|
||||
QT_BASE_DIR="/home/ari/sie/p/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.7.0"
|
||||
${QT_BASE_DIR}/bin/qmake -spec ${QT_BASE_DIR}/mkspecs/qws/linux-openwrt-g++ -o Makefile
|
||||
make
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<RCC>
|
||||
<qresource prefix="/new/prefix1">
|
||||
<file>images/copy.png</file>
|
||||
<file>images/cut.png</file>
|
||||
<file>images/new.png</file>
|
||||
<file>images/open.png</file>
|
||||
<file>images/paste.png</file>
|
||||
<file>images/save.png</file>
|
||||
</qresource>
|
||||
</RCC>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 1.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 852 B |
Binary file not shown.
|
After Width: | Height: | Size: 2.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.6 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.2 KiB |
|
|
@ -0,0 +1,11 @@
|
|||
#include <QtGui/QApplication>
|
||||
#include "mainwindow.h"
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
QApplication a(argc, argv);
|
||||
MainWindow w;
|
||||
w.show();
|
||||
|
||||
return a.exec();
|
||||
}
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
#include <QtGui>
|
||||
#include <QMainWindow>
|
||||
#include "mainwindow.h"
|
||||
#include "ui_mainwindow.h"
|
||||
|
||||
MainWindow::MainWindow(QWidget *parent) :
|
||||
QMainWindow(parent),
|
||||
ui(new Ui::MainWindow)
|
||||
{
|
||||
ui->setupUi(this);
|
||||
}
|
||||
|
||||
MainWindow::~MainWindow()
|
||||
{
|
||||
delete ui;
|
||||
}
|
||||
|
||||
void MainWindow::newfile(){
|
||||
|
||||
if (maybeSave()) {
|
||||
ui->textEdit->clear();
|
||||
setCurrentFile("");
|
||||
}
|
||||
}
|
||||
|
||||
bool MainWindow::maybeSave(){
|
||||
|
||||
if (ui->textEdit->document()->isModified()) {
|
||||
QMessageBox::StandardButton ret;
|
||||
ret = QMessageBox::warning(this, tr("Application"),
|
||||
tr("The document has been modified.\n"
|
||||
"Do you want to save your changes?"),
|
||||
QMessageBox::Save | QMessageBox::Discard | QMessageBox::Cancel);
|
||||
if (ret == QMessageBox::Save)
|
||||
return save();
|
||||
else if (ret == QMessageBox::Cancel)
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void MainWindow::setCurrentFile(const QString &fileName){
|
||||
|
||||
curFile = fileName;
|
||||
ui->textEdit->document()->setModified(false);
|
||||
setWindowModified(false);
|
||||
|
||||
QString shownName = curFile;
|
||||
if (curFile.isEmpty())
|
||||
shownName = "untitled.txt";
|
||||
setWindowFilePath(shownName);
|
||||
}
|
||||
|
||||
bool MainWindow::save(){
|
||||
|
||||
if (curFile.isEmpty()) {
|
||||
return saveAs();
|
||||
} else {
|
||||
return saveFile(curFile);
|
||||
}
|
||||
}
|
||||
|
||||
bool MainWindow::saveAs(){
|
||||
|
||||
QString fileName = QFileDialog::getSaveFileName(this);
|
||||
if (fileName.isEmpty())
|
||||
return false;
|
||||
|
||||
return saveFile(fileName);
|
||||
}
|
||||
|
||||
bool MainWindow::saveFile(const QString &fileName){
|
||||
|
||||
QFile file(fileName);
|
||||
if (!file.open(QFile::WriteOnly | QFile::Text)) {
|
||||
QMessageBox::warning(this, tr("Application"),
|
||||
tr("Cannot write file %1:\n%2.")
|
||||
.arg(fileName)
|
||||
.arg(file.errorString()));
|
||||
return false;
|
||||
}
|
||||
|
||||
QTextStream out(&file);
|
||||
#ifndef QT_NO_CURSOR
|
||||
QApplication::setOverrideCursor(Qt::WaitCursor);
|
||||
#endif
|
||||
out << ui->textEdit->toPlainText();
|
||||
#ifndef QT_NO_CURSOR
|
||||
QApplication::restoreOverrideCursor();
|
||||
#endif
|
||||
|
||||
setCurrentFile(fileName);
|
||||
statusBar()->showMessage(tr("File saved"), 2000);
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
#ifndef MAINWINDOW_H
|
||||
#define MAINWINDOW_H
|
||||
|
||||
#include <QMainWindow>
|
||||
|
||||
namespace Ui {
|
||||
class MainWindow;
|
||||
}
|
||||
|
||||
class MainWindow : public QMainWindow
|
||||
{
|
||||
Q_OBJECT
|
||||
|
||||
public:
|
||||
explicit MainWindow(QWidget *parent = 0);
|
||||
~MainWindow();
|
||||
|
||||
private slots:
|
||||
void newfile();
|
||||
bool save();
|
||||
bool saveAs();
|
||||
|
||||
private:
|
||||
Ui::MainWindow *ui;
|
||||
bool maybeSave();
|
||||
void setCurrentFile(const QString &fileName);
|
||||
bool saveFile(const QString &fileName);
|
||||
QString curFile;
|
||||
};
|
||||
|
||||
#endif // MAINWINDOW_H
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ui version="4.0">
|
||||
<class>MainWindow</class>
|
||||
<widget class="QMainWindow" name="MainWindow">
|
||||
<property name="geometry">
|
||||
<rect>
|
||||
<x>0</x>
|
||||
<y>0</y>
|
||||
<width>320</width>
|
||||
<height>240</height>
|
||||
</rect>
|
||||
</property>
|
||||
<property name="windowTitle">
|
||||
<string>MainWindow</string>
|
||||
</property>
|
||||
<widget class="QWidget" name="centralWidget">
|
||||
<widget class="QScrollArea" name="scrollArea">
|
||||
<property name="geometry">
|
||||
<rect>
|
||||
<x>-11</x>
|
||||
<y>-10</y>
|
||||
<width>341</width>
|
||||
<height>211</height>
|
||||
</rect>
|
||||
</property>
|
||||
<property name="widgetResizable">
|
||||
<bool>true</bool>
|
||||
</property>
|
||||
<widget class="QWidget" name="scrollAreaWidgetContents">
|
||||
<property name="geometry">
|
||||
<rect>
|
||||
<x>0</x>
|
||||
<y>0</y>
|
||||
<width>335</width>
|
||||
<height>205</height>
|
||||
</rect>
|
||||
</property>
|
||||
<widget class="QTextEdit" name="textEdit">
|
||||
<property name="geometry">
|
||||
<rect>
|
||||
<x>7</x>
|
||||
<y>6</y>
|
||||
<width>322</width>
|
||||
<height>170</height>
|
||||
</rect>
|
||||
</property>
|
||||
</widget>
|
||||
</widget>
|
||||
</widget>
|
||||
</widget>
|
||||
<widget class="QMenuBar" name="menuBar">
|
||||
<property name="geometry">
|
||||
<rect>
|
||||
<x>0</x>
|
||||
<y>0</y>
|
||||
<width>320</width>
|
||||
<height>21</height>
|
||||
</rect>
|
||||
</property>
|
||||
<widget class="QMenu" name="menuFile">
|
||||
<property name="title">
|
||||
<string>&File</string>
|
||||
</property>
|
||||
<addaction name="actionNew"/>
|
||||
<addaction name="actionOpen"/>
|
||||
<addaction name="actionSave"/>
|
||||
<addaction name="actionSave_As"/>
|
||||
<addaction name="separator"/>
|
||||
<addaction name="actionExit"/>
|
||||
</widget>
|
||||
<widget class="QMenu" name="menuHelp">
|
||||
<property name="title">
|
||||
<string>&Help</string>
|
||||
</property>
|
||||
<addaction name="actionAbout"/>
|
||||
</widget>
|
||||
<widget class="QMenu" name="menuEdit">
|
||||
<property name="title">
|
||||
<string>&Edit</string>
|
||||
</property>
|
||||
<addaction name="actionCut"/>
|
||||
<addaction name="actionCopy"/>
|
||||
<addaction name="actionPaste"/>
|
||||
</widget>
|
||||
<addaction name="menuFile"/>
|
||||
<addaction name="menuEdit"/>
|
||||
<addaction name="menuHelp"/>
|
||||
</widget>
|
||||
<widget class="QToolBar" name="mainToolBar">
|
||||
<attribute name="toolBarArea">
|
||||
<enum>TopToolBarArea</enum>
|
||||
</attribute>
|
||||
<attribute name="toolBarBreak">
|
||||
<bool>false</bool>
|
||||
</attribute>
|
||||
<addaction name="actionNew"/>
|
||||
<addaction name="actionOpen"/>
|
||||
<addaction name="actionSave"/>
|
||||
<addaction name="actionCut"/>
|
||||
<addaction name="actionCopy"/>
|
||||
<addaction name="actionPaste"/>
|
||||
</widget>
|
||||
<widget class="QStatusBar" name="statusBar"/>
|
||||
<action name="actionNew">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/new.png</normaloff>:/new/prefix1/images/new.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>&New</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Create a new file</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+N</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionOpen">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/open.png</normaloff>
|
||||
<normalon>images/open.png</normalon>:/new/prefix1/images/open.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>&Open</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Open an existing file</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+O</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionSave">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/save.png</normaloff>:/new/prefix1/images/save.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>&Save</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Save the document to disk</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+S</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionSave_As">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/save.png</normaloff>:/new/prefix1/images/save.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>Save &As...</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Save the document under a new name</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionExit">
|
||||
<property name="text">
|
||||
<string>E&xit</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Exit the application</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+Q</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionCut">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/cut.png</normaloff>:/new/prefix1/images/cut.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>Cu&t</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Cut the current selection's contents to the clipboard</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+X</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionCopy">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/copy.png</normaloff>:/new/prefix1/images/copy.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>&Copy</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Copy the current selection's contents to the clipboard</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+C</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionPaste">
|
||||
<property name="icon">
|
||||
<iconset resource="images.qrc">
|
||||
<normaloff>:/new/prefix1/images/paste.png</normaloff>:/new/prefix1/images/paste.png</iconset>
|
||||
</property>
|
||||
<property name="text">
|
||||
<string>&Paste</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Paste the clipboard's contents into the current selection</string>
|
||||
</property>
|
||||
<property name="shortcut">
|
||||
<string>Ctrl+V</string>
|
||||
</property>
|
||||
</action>
|
||||
<action name="actionAbout">
|
||||
<property name="text">
|
||||
<string>&About</string>
|
||||
</property>
|
||||
<property name="statusTip">
|
||||
<string>Show the application's About box</string>
|
||||
</property>
|
||||
</action>
|
||||
</widget>
|
||||
<layoutdefault spacing="6" margin="11"/>
|
||||
<tabstops>
|
||||
<tabstop>textEdit</tabstop>
|
||||
<tabstop>scrollArea</tabstop>
|
||||
</tabstops>
|
||||
<resources>
|
||||
<include location="images.qrc"/>
|
||||
</resources>
|
||||
<connections>
|
||||
<connection>
|
||||
<sender>actionCut</sender>
|
||||
<signal>triggered()</signal>
|
||||
<receiver>textEdit</receiver>
|
||||
<slot>cut()</slot>
|
||||
<hints>
|
||||
<hint type="sourcelabel">
|
||||
<x>-1</x>
|
||||
<y>-1</y>
|
||||
</hint>
|
||||
<hint type="destinationlabel">
|
||||
<x>159</x>
|
||||
<y>123</y>
|
||||
</hint>
|
||||
</hints>
|
||||
</connection>
|
||||
<connection>
|
||||
<sender>actionCopy</sender>
|
||||
<signal>triggered()</signal>
|
||||
<receiver>textEdit</receiver>
|
||||
<slot>copy()</slot>
|
||||
<hints>
|
||||
<hint type="sourcelabel">
|
||||
<x>-1</x>
|
||||
<y>-1</y>
|
||||
</hint>
|
||||
<hint type="destinationlabel">
|
||||
<x>159</x>
|
||||
<y>123</y>
|
||||
</hint>
|
||||
</hints>
|
||||
</connection>
|
||||
<connection>
|
||||
<sender>actionExit</sender>
|
||||
<signal>triggered()</signal>
|
||||
<receiver>MainWindow</receiver>
|
||||
<slot>close()</slot>
|
||||
<hints>
|
||||
<hint type="sourcelabel">
|
||||
<x>-1</x>
|
||||
<y>-1</y>
|
||||
</hint>
|
||||
<hint type="destinationlabel">
|
||||
<x>159</x>
|
||||
<y>119</y>
|
||||
</hint>
|
||||
</hints>
|
||||
</connection>
|
||||
<connection>
|
||||
<sender>actionPaste</sender>
|
||||
<signal>triggered()</signal>
|
||||
<receiver>textEdit</receiver>
|
||||
<slot>paste()</slot>
|
||||
<hints>
|
||||
<hint type="sourcelabel">
|
||||
<x>-1</x>
|
||||
<y>-1</y>
|
||||
</hint>
|
||||
<hint type="destinationlabel">
|
||||
<x>159</x>
|
||||
<y>123</y>
|
||||
</hint>
|
||||
</hints>
|
||||
</connection>
|
||||
<connection>
|
||||
<sender>actionNew</sender>
|
||||
<signal>triggered()</signal>
|
||||
<receiver>MainWindow</receiver>
|
||||
<slot>newfile()</slot>
|
||||
<hints>
|
||||
<hint type="sourcelabel">
|
||||
<x>16</x>
|
||||
<y>11</y>
|
||||
</hint>
|
||||
<hint type="destinationlabel">
|
||||
<x>159</x>
|
||||
<y>119</y>
|
||||
</hint>
|
||||
</hints>
|
||||
</connection>
|
||||
</connections>
|
||||
<slots>
|
||||
<slot>newfile()</slot>
|
||||
</slots>
|
||||
</ui>
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
DESIGN = uart_peripheral
|
||||
PINS = $(DESIGN).ucf
|
||||
DEVICE = xc3s500e-VQ100-4
|
||||
BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
|
||||
-g CRC:enable -g StartUpClk:CCLK
|
||||
|
||||
SIM_CMD = vsim
|
||||
SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
|
||||
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
|
||||
IVERILOG = iverilog
|
||||
|
||||
SAKC_IP = 192.168.254.101
|
||||
|
||||
SRC = uart_peripheral.v \
|
||||
uart.v
|
||||
|
||||
SIM_SRC =uart_peripheral.v\
|
||||
|
||||
|
||||
all: bits
|
||||
|
||||
remake: clean-build all
|
||||
|
||||
clean:
|
||||
rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
|
||||
rm -f *.bit
|
||||
|
||||
cleanall: clean
|
||||
rm -rf build simulation/work simulation/transcript simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
|
||||
|
||||
bits: $(DESIGN).bit
|
||||
|
||||
#
|
||||
# Synthesis
|
||||
#
|
||||
build/project.src:
|
||||
@[ -d build ] || mkdir build
|
||||
@rm -f $@
|
||||
for i in $(SRC); do echo verilog work ../$$i >> $@; done
|
||||
for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
|
||||
|
||||
build/project.xst: build/project.src
|
||||
echo "run" > $@
|
||||
echo "-top $(DESIGN) " >> $@
|
||||
echo "-p $(DEVICE)" >> $@
|
||||
echo "-opt_mode Area" >> $@
|
||||
echo "-opt_level 1" >> $@
|
||||
echo "-ifn project.src" >> $@
|
||||
echo "-ifmt mixed" >> $@
|
||||
echo "-ofn project.ngc" >> $@
|
||||
echo "-ofmt NGC" >> $@
|
||||
echo "-rtlview yes" >> $@
|
||||
|
||||
build/project.ngc: build/project.xst $(SRC)
|
||||
cd build && xst -ifn project.xst -ofn project.log
|
||||
|
||||
build/project.ngd: build/project.ngc $(PINS)
|
||||
cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
|
||||
|
||||
build/project.ncd: build/project.ngd
|
||||
cd build && map -pr b -p $(DEVICE) project
|
||||
|
||||
build/project_r.ncd: build/project.ncd
|
||||
cd build && par -w project project_r.ncd
|
||||
|
||||
build/project_r.twr: build/project_r.ncd
|
||||
cd build && trce -v 25 project_r.ncd project.pcf
|
||||
|
||||
$(DESIGN).bit: build/project_r.ncd build/project_r.twr
|
||||
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
|
||||
@mv -f build/project_r.bit $@
|
||||
|
||||
build/project_r.v: build/project_r.ncd
|
||||
cd build && ngd2ver project.ngd -w project.v
|
||||
|
||||
modelsim:
|
||||
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
|
||||
|
||||
timesim: build/project_r.v
|
||||
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
|
||||
|
||||
iversim:
|
||||
$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
|
||||
vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
|
||||
gtkwave simulation/$(DESIGN)_TB.vcd&
|
||||
|
||||
upload: $(DESIGN).bit
|
||||
scp $(DESIGN).bit root@$(SAKC_IP):binaries
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/UART/logic/build/project.ngc 1289504255
|
||||
OK
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
Release 10.1.03 ngdbuild K.39 (lin)
|
||||
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: /opt/cad/Xilinx/10.1/ISE/bin/lin/unwrapped/ngdbuild -p
|
||||
xc3s500e-VQ100-4 project.ngc -uc ../uart_peripheral.ucf
|
||||
|
||||
Reading NGO file
|
||||
"/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/UART/logic/build/project.ngc" ...
|
||||
Gathering constraint information from source properties...
|
||||
Done.
|
||||
|
||||
Applying constraints in "../uart_peripheral.ucf" to the design...
|
||||
Resolving constraint associations...
|
||||
Checking Constraint Associations...
|
||||
Done...
|
||||
Checking Partitions ...
|
||||
|
||||
Checking expanded design ...
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 60312 kilobytes
|
||||
|
||||
Writing NGD file "project.ngd" ...
|
||||
|
||||
Writing NGDBUILD log file "project.bld"...
|
||||
|
|
@ -0,0 +1,690 @@
|
|||
Release 10.1.03 - xst K.39 (lin)
|
||||
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
||||
-->
|
||||
PMSPEC -- Overriding Xilinx file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd> with local file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd>
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) Design Hierarchy Analysis
|
||||
4) HDL Analysis
|
||||
5) HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Advanced HDL Synthesis
|
||||
6.1) Advanced HDL Synthesis Report
|
||||
7) Low Level Synthesis
|
||||
8) Partition Report
|
||||
9) Final Report
|
||||
9.1) Device utilization summary
|
||||
9.2) Partition Resource Summary
|
||||
9.3) TIMING REPORT
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "project.src"
|
||||
Input Format : mixed
|
||||
|
||||
---- Target Parameters
|
||||
Target Device : xc3s500e-VQ100-4
|
||||
Output File Name : "project.ngc"
|
||||
Output Format : NGC
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : uart_peripheral
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Area
|
||||
Optimization Effort : 1
|
||||
RTL Output : yes
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling verilog file "../uart_peripheral.v" in library work
|
||||
Compiling verilog file "../uart.v" in library work
|
||||
Module <uart_peripheral> compiled
|
||||
Module <UART> compiled
|
||||
Module <pc_buffrx_pc> compiled
|
||||
Module <pc_bufftx> compiled
|
||||
Module <pc_ctrl_rx> compiled
|
||||
Module <pc_ctrl_tx_pc> compiled
|
||||
Module <pc_dato_rdy> compiled
|
||||
Module <pc_div27> compiled
|
||||
Module <pc_div16> compiled
|
||||
Module <pc_div_ms> compiled
|
||||
Module <pc_ier> compiled
|
||||
Module <pc_if_arm_pc> compiled
|
||||
Module <pc_ifrxd> compiled
|
||||
Module <pc_isr> compiled
|
||||
Module <pc_lcr> compiled
|
||||
Module <pc_muestreo> compiled
|
||||
Module <pc_pulso> compiled
|
||||
No errors in compilation
|
||||
Analysis of file <"project.src"> succeeded.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for module <uart_peripheral> in library <work> with parameters.
|
||||
B = "00000000000000000000000000000111"
|
||||
|
||||
Analyzing hierarchy for module <UART> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_if_arm_pc> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_div27> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_div_ms> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_pulso> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_div16> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_ifrxd> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_muestreo> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_buffrx_pc> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_ctrl_rx> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_dato_rdy> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_bufftx> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_ctrl_tx_pc> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_ier> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_lcr> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <pc_isr> in library <work>.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing top module <uart_peripheral>.
|
||||
B = 32'sb00000000000000000000000000000111
|
||||
WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CD' of instance 'UART' is tied to GND.
|
||||
WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'RI' of instance 'UART' is tied to GND.
|
||||
WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'DSR' of instance 'UART' is tied to GND.
|
||||
WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CTS' of instance 'UART' is tied to GND.
|
||||
Module <uart_peripheral> is correct for synthesis.
|
||||
|
||||
Analyzing module <UART> in library <work>.
|
||||
Module <UART> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_if_arm_pc> in library <work>.
|
||||
Module <pc_if_arm_pc> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_div27> in library <work>.
|
||||
Module <pc_div27> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_div_ms> in library <work>.
|
||||
Module <pc_div_ms> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_pulso> in library <work>.
|
||||
Module <pc_pulso> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_div16> in library <work>.
|
||||
Module <pc_div16> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_ifrxd> in library <work>.
|
||||
Module <pc_ifrxd> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_muestreo> in library <work>.
|
||||
Module <pc_muestreo> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_buffrx_pc> in library <work>.
|
||||
Module <pc_buffrx_pc> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_ctrl_rx> in library <work>.
|
||||
Module <pc_ctrl_rx> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_dato_rdy> in library <work>.
|
||||
Module <pc_dato_rdy> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_bufftx> in library <work>.
|
||||
Module <pc_bufftx> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_ctrl_tx_pc> in library <work>.
|
||||
Module <pc_ctrl_tx_pc> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_ier> in library <work>.
|
||||
Module <pc_ier> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_lcr> in library <work>.
|
||||
Module <pc_lcr> is correct for synthesis.
|
||||
|
||||
Analyzing module <pc_isr> in library <work>.
|
||||
Module <pc_isr> is correct for synthesis.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
INFO:Xst:2679 - Register <buftx<10>> in unit <pc_bufftx> has a constant value of 1 during circuit operation. The register is replaced by logic.
|
||||
|
||||
Synthesizing Unit <pc_if_arm_pc>.
|
||||
Related source file is "../uart.v".
|
||||
WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <data_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
Unit <pc_if_arm_pc> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_div27>.
|
||||
Related source file is "../uart.v".
|
||||
Found 6-bit up counter for signal <div27>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
Unit <pc_div27> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_div_ms>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <clk_out>.
|
||||
Found 16-bit register for signal <div>.
|
||||
Found 16-bit adder for signal <div$addsub0000> created at line 581.
|
||||
Found 16-bit comparator equal for signal <div$cmp_eq0000> created at line 574.
|
||||
Found 16-bit register for signal <k_div>.
|
||||
Summary:
|
||||
inferred 33 D-type flip-flop(s).
|
||||
inferred 1 Adder/Subtractor(s).
|
||||
inferred 1 Comparator(s).
|
||||
Unit <pc_div_ms> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_pulso>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <dff>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <pc_pulso> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_div16>.
|
||||
Related source file is "../uart.v".
|
||||
Found 4-bit up counter for signal <div16>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
Unit <pc_div16> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_ifrxd>.
|
||||
Related source file is "../uart.v".
|
||||
Found 3-bit register for signal <ifrxd>.
|
||||
Found 1-bit xor2 for signal <ifrxd_2$xor0000> created at line 967.
|
||||
Found 1-bit xor2 for signal <ifrxd_2$xor0001> created at line 967.
|
||||
Summary:
|
||||
inferred 3 D-type flip-flop(s).
|
||||
Unit <pc_ifrxd> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_muestreo>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <sample>.
|
||||
Found 4-bit up counter for signal <cont_m>.
|
||||
Found 1-bit register for signal <flag_rx>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <pc_muestreo> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_buffrx_pc>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <err_paridad>.
|
||||
Found 8-bit register for signal <datorx>.
|
||||
Found 1-bit register for signal <err_frame>.
|
||||
Found 10-bit register for signal <bufrx>.
|
||||
Found 1-bit xor9 for signal <iparity>.
|
||||
Summary:
|
||||
inferred 20 D-type flip-flop(s).
|
||||
inferred 1 Xor(s).
|
||||
Unit <pc_buffrx_pc> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_ctrl_rx>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <rx_lleno>.
|
||||
Found 4-bit up counter for signal <cont_rx>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <pc_ctrl_rx> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_dato_rdy>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <dato_rdy>.
|
||||
Found 1-bit register for signal <err_overrun>.
|
||||
Summary:
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <pc_dato_rdy> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_bufftx>.
|
||||
Related source file is "../uart.v".
|
||||
Found 10-bit register for signal <buftx<9:0>>.
|
||||
Found 8-bit register for signal <dato_tx>.
|
||||
Found 1-bit xor8 for signal <iparity>.
|
||||
Summary:
|
||||
inferred 18 D-type flip-flop(s).
|
||||
inferred 1 Xor(s).
|
||||
Unit <pc_bufftx> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_ctrl_tx_pc>.
|
||||
Related source file is "../uart.v".
|
||||
Found 1-bit register for signal <tx_empty>.
|
||||
Found 4-bit up counter for signal <cont_tx>.
|
||||
Found 1-bit register for signal <tx_on>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <pc_ctrl_tx_pc> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_ier>.
|
||||
Related source file is "../uart.v".
|
||||
WARNING:Xst:647 - Input <data_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 4-bit register for signal <IER>.
|
||||
Summary:
|
||||
inferred 4 D-type flip-flop(s).
|
||||
Unit <pc_ier> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_lcr>.
|
||||
Related source file is "../uart.v".
|
||||
Found 8-bit register for signal <LCR>.
|
||||
Summary:
|
||||
inferred 8 D-type flip-flop(s).
|
||||
Unit <pc_lcr> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <pc_isr>.
|
||||
Related source file is "../uart.v".
|
||||
WARNING:Xst:647 - Input <IER<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:646 - Signal <err_overrunm> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
Found 4-bit register for signal <ISR>.
|
||||
Found 1-bit register for signal <aux1>.
|
||||
Found 1-bit register for signal <carga_ISRd>.
|
||||
Found 1-bit register for signal <mask_dato_rdy>.
|
||||
Found 1-bit register for signal <mask_err_overrun>.
|
||||
Found 1-bit register for signal <mask_error>.
|
||||
Found 1-bit register for signal <mask_modem_int>.
|
||||
Found 1-bit register for signal <mask_tx_empty>.
|
||||
Summary:
|
||||
inferred 11 D-type flip-flop(s).
|
||||
Unit <pc_isr> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <UART>.
|
||||
Related source file is "../uart.v".
|
||||
WARNING:Xst:647 - Input <CD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:1305 - Output <RTS> is never assigned. Tied to value 0.
|
||||
WARNING:Xst:647 - Input <CTS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:647 - Input <DSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:1305 - Output <DTR> is never assigned. Tied to value 0.
|
||||
WARNING:Xst:647 - Input <RI> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:653 - Signal <modem_int> is used but never assigned. This sourceless signal will be automatically connected to value 0.
|
||||
WARNING:Xst:653 - Signal <modem> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
||||
WARNING:Xst:1780 - Signal <error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:1780 - Signal <carga_div> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <carga_MSR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <carga_MCR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <WordLength> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <Stop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
Unit <UART> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <uart_peripheral>.
|
||||
Related source file is "../uart_peripheral.v".
|
||||
WARNING:Xst:647 - Input <RxD2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
WARNING:Xst:1306 - Output <TxD2> is never assigned.
|
||||
WARNING:Xst:646 - Signal <out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:646 - Signal <buffer_addr<12:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:1780 - Signal <RD> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
WARNING:Xst:1780 - Signal <ISRC_LP> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
||||
Found 8-bit tristate buffer for signal <sram_data>.
|
||||
Found 13-bit register for signal <buffer_addr>.
|
||||
Found 8-bit register for signal <buffer_data>.
|
||||
Found 24-bit up counter for signal <counter>.
|
||||
Found 1-bit register for signal <sncs>.
|
||||
Found 1-bit register for signal <snwe>.
|
||||
Found 1-bit register for signal <w_st>.
|
||||
Found 8-bit register for signal <wdBus>.
|
||||
Found 1-bit register for signal <we>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 33 D-type flip-flop(s).
|
||||
inferred 8 Tristate(s).
|
||||
Unit <uart_peripheral> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 1
|
||||
16-bit adder : 1
|
||||
# Counters : 6
|
||||
24-bit up counter : 1
|
||||
4-bit up counter : 4
|
||||
6-bit up counter : 1
|
||||
# Registers : 71
|
||||
1-bit register : 62
|
||||
13-bit register : 1
|
||||
16-bit register : 1
|
||||
4-bit register : 2
|
||||
8-bit register : 5
|
||||
# Comparators : 1
|
||||
16-bit comparator equal : 1
|
||||
# Tristates : 1
|
||||
8-bit tristate buffer : 1
|
||||
# Xors : 4
|
||||
1-bit xor2 : 2
|
||||
1-bit xor8 : 1
|
||||
1-bit xor9 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/cad/Xilinx/10.1/ISE:/opt/cad/Xilinx/10.1/ISE/.
|
||||
WARNING:Xst:1710 - FF/Latch <ISR_3> (without init value) has a constant value of 0 in block <pc_isr>. This FF/Latch will be trimmed during the optimization process.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_3> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_4> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_5> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_6> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_7> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_8> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_9> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_10> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_11> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <buffer_addr_12> of sequential type is unconnected in block <uart_peripheral>.
|
||||
WARNING:Xst:2677 - Node <IER_3> of sequential type is unconnected in block <ier1>.
|
||||
WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <isr1>.
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 1
|
||||
16-bit adder : 1
|
||||
# Counters : 6
|
||||
24-bit up counter : 1
|
||||
4-bit up counter : 4
|
||||
6-bit up counter : 1
|
||||
# Registers : 128
|
||||
Flip-Flops : 128
|
||||
# Comparators : 1
|
||||
16-bit comparator equal : 1
|
||||
# Xors : 4
|
||||
1-bit xor2 : 2
|
||||
1-bit xor8 : 1
|
||||
1-bit xor9 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <pc_isr>.
|
||||
|
||||
Optimizing unit <uart_peripheral> ...
|
||||
|
||||
Optimizing unit <pc_div_ms> ...
|
||||
|
||||
Optimizing unit <pc_buffrx_pc> ...
|
||||
|
||||
Optimizing unit <pc_bufftx> ...
|
||||
|
||||
Optimizing unit <pc_isr> ...
|
||||
WARNING:Xst:2677 - Node <UART/ier1/IER_3> of sequential type is unconnected in block <uart_peripheral>.
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
FlipFlop counter_23 has been replicated 1 time(s) to handle iob=true attribute.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
=========================================================================
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 173
|
||||
Flip-Flops : 173
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : project.ngr
|
||||
Top Level Output File Name : project.ngc
|
||||
Output Format : NGC
|
||||
Optimization Goal : Area
|
||||
Keep Hierarchy : no
|
||||
|
||||
Design Statistics
|
||||
# IOs : 22
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 278
|
||||
# GND : 1
|
||||
# INV : 9
|
||||
# LUT1 : 38
|
||||
# LUT2 : 10
|
||||
# LUT3 : 48
|
||||
# LUT4 : 78
|
||||
# MUXCY : 46
|
||||
# MUXF5 : 7
|
||||
# VCC : 1
|
||||
# XORCY : 40
|
||||
# FlipFlops/Latches : 173
|
||||
# FD : 3
|
||||
# FD_1 : 13
|
||||
# FDC : 10
|
||||
# FDCE : 80
|
||||
# FDE : 1
|
||||
# FDP : 1
|
||||
# FDPE : 14
|
||||
# FDR : 36
|
||||
# FDRE : 12
|
||||
# FDSE : 3
|
||||
# Clock Buffers : 1
|
||||
# BUFGP : 1
|
||||
# IO Buffers : 19
|
||||
# IBUF : 8
|
||||
# IOBUF : 8
|
||||
# OBUF : 3
|
||||
=========================================================================
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 3s500evq100-4
|
||||
|
||||
Number of Slices: 114 out of 4656 2%
|
||||
Number of Slice Flip Flops: 158 out of 9312 1%
|
||||
Number of 4 input LUTs: 183 out of 9312 1%
|
||||
Number of IOs: 22
|
||||
Number of bonded IOBs: 20 out of 66 30%
|
||||
IOB Flip Flops: 15
|
||||
Number of GCLKs: 1 out of 24 4%
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
---------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
---------------------------
|
||||
|
||||
|
||||
=========================================================================
|
||||
TIMING REPORT
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
GENERATED AFTER PLACE-and-ROUTE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
-----------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+------------------------+-------+
|
||||
clk | BUFGP | 173 |
|
||||
-----------------------------------+------------------------+-------+
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
-----------------------------------+---------------------------+-------+
|
||||
Control Signal | Buffer(FF name) | Load |
|
||||
-----------------------------------+---------------------------+-------+
|
||||
reset_inv(reset_inv1_INV_0:O) | NONE(UART/bufftx1/buftx_9)| 105 |
|
||||
-----------------------------------+---------------------------+-------+
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -4
|
||||
|
||||
Minimum period: 13.338ns (Maximum Frequency: 74.974MHz)
|
||||
Minimum input arrival time before clock: 4.803ns
|
||||
Maximum output required time after clock: 9.916ns
|
||||
Maximum combinational path delay: 6.573ns
|
||||
|
||||
Timing Detail:
|
||||
--------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'clk'
|
||||
Clock period: 13.338ns (frequency: 74.974MHz)
|
||||
Total number of paths / destination ports: 2891 / 269
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 6.669ns (Levels of Logic = 3)
|
||||
Source: buffer_addr_1 (FF)
|
||||
Destination: UART/div_ms1/div_15 (FF)
|
||||
Source Clock: clk falling
|
||||
Destination Clock: clk rising
|
||||
|
||||
Data Path: buffer_addr_1 to UART/div_ms1/div_15
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD_1:C->Q 13 0.591 0.987 buffer_addr_1 (buffer_addr_1)
|
||||
LUT4:I3->O 3 0.704 0.566 UART/if_arm1/data_out_cmp_eq00001 (UART/if_arm1/data_out_cmp_eq0000)
|
||||
LUT3:I2->O 9 0.704 0.824 UART/if_arm1/carga_div_low1 (UART/carga_div_low)
|
||||
LUT4:I3->O 16 0.704 1.034 UART/div_ms1/div_not00021 (UART/div_ms1/div_not0002)
|
||||
FDCE:CE 0.555 UART/div_ms1/div_0
|
||||
----------------------------------------
|
||||
Total 6.669ns (3.258ns logic, 3.411ns route)
|
||||
(48.9% logic, 51.1% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
|
||||
Total number of paths / destination ports: 69 / 69
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.803ns (Levels of Logic = 2)
|
||||
Source: reset (PAD)
|
||||
Destination: w_st (FF)
|
||||
Destination Clock: clk rising
|
||||
|
||||
Data Path: reset to w_st
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 6 1.218 0.669 reset_IBUF (reset_IBUF)
|
||||
INV:I->O 155 0.704 1.301 reset_inv1_INV_0 (reset_inv)
|
||||
FDR:R 0.911 w_st
|
||||
----------------------------------------
|
||||
Total 4.803ns (2.833ns logic, 1.970ns route)
|
||||
(59.0% logic, 41.0% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
|
||||
Total number of paths / destination ports: 169 / 11
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 9.916ns (Levels of Logic = 5)
|
||||
Source: buffer_addr_0 (FF)
|
||||
Destination: sram_data<2> (PAD)
|
||||
Source Clock: clk falling
|
||||
|
||||
Data Path: buffer_addr_0 to sram_data<2>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FD_1:C->Q 5 0.591 0.808 buffer_addr_0 (buffer_addr_0)
|
||||
LUT2:I0->O 2 0.704 0.482 UART/if_arm1/data_out_or000111 (N6)
|
||||
LUT4:I2->O 8 0.704 0.932 UART/if_arm1/data_out<0>11 (N01)
|
||||
LUT4:I0->O 1 0.704 0.595 UART/if_arm1/data_out<2>4 (UART/if_arm1/data_out<2>4)
|
||||
LUT4:I0->O 1 0.704 0.420 UART/if_arm1/data_out<2>14 (rdBus<2>)
|
||||
IOBUF:I->IO 3.272 sram_data_2_IOBUF (sram_data<2>)
|
||||
----------------------------------------
|
||||
Total 9.916ns (6.679ns logic, 3.237ns route)
|
||||
(67.4% logic, 32.6% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 16 / 8
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 6.573ns (Levels of Logic = 3)
|
||||
Source: ncs (PAD)
|
||||
Destination: sram_data<7> (PAD)
|
||||
|
||||
Data Path: ncs to sram_data<7>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 2 1.218 0.622 ncs_IBUF (ncs_IBUF)
|
||||
LUT2:I0->O 8 0.704 0.757 T1 (T)
|
||||
IOBUF:T->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
|
||||
----------------------------------------
|
||||
Total 6.573ns (5.194ns logic, 1.379ns route)
|
||||
(79.0% logic, 21.0% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 28.00 secs
|
||||
Total CPU time to Xst completion: 24.17 secs
|
||||
|
||||
-->
|
||||
|
||||
|
||||
Total memory usage is 143224 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 49 ( 0 filtered)
|
||||
Number of infos : 1 ( 0 filtered)
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
Release 10.1.03 Map K.39 (lin)
|
||||
Xilinx Map Application Log File for Design 'uart_peripheral'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
|
||||
Target Device : xc3s500e
|
||||
Target Package : vq100
|
||||
Target Speed : -4
|
||||
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
|
||||
Mapped Date : Thu Nov 11 14:37:58 2010
|
||||
|
||||
Mapping design into LUTs...
|
||||
Writing file project.ngm...
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Running related packing...
|
||||
Writing design file "project.ncd"...
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 2
|
||||
Logic Utilization:
|
||||
Number of Slice Flip Flops: 157 out of 9,312 1%
|
||||
Number of 4 input LUTs: 141 out of 9,312 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 138 out of 4,656 2%
|
||||
Number of Slices containing only related logic: 138 out of 138 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 138 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 181 out of 9,312 1%
|
||||
Number used as logic: 141
|
||||
Number used as a route-thru: 40
|
||||
Number of bonded IOBs: 20 out of 66 30%
|
||||
IOB Flip Flops: 16
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Peak Memory Usage: 152 MB
|
||||
Total REAL time to MAP completion: 10 secs
|
||||
Total CPU time to MAP completion: 8 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "project.mrp" for details.
|
||||
|
|
@ -0,0 +1,207 @@
|
|||
Release 10.1.03 Map K.39 (lin)
|
||||
Xilinx Mapping Report File for Design 'uart_peripheral'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
|
||||
Target Device : xc3s500e
|
||||
Target Package : vq100
|
||||
Target Speed : -4
|
||||
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
|
||||
Mapped Date : Thu Nov 11 14:37:58 2010
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 2
|
||||
Logic Utilization:
|
||||
Number of Slice Flip Flops: 157 out of 9,312 1%
|
||||
Number of 4 input LUTs: 141 out of 9,312 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 138 out of 4,656 2%
|
||||
Number of Slices containing only related logic: 138 out of 138 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 138 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 181 out of 9,312 1%
|
||||
Number used as logic: 141
|
||||
Number used as a route-thru: 40
|
||||
Number of bonded IOBs: 20 out of 66 30%
|
||||
IOB Flip Flops: 16
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Peak Memory Usage: 152 MB
|
||||
Total REAL time to MAP completion: 10 secs
|
||||
Total CPU time to MAP completion: 8 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Modular Design Summary
|
||||
Section 11 - Timing Report
|
||||
Section 12 - Configuration String Information
|
||||
Section 13 - Control Set Information
|
||||
Section 14 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
WARNING:LIT:243 - Logical network RxD2 has no load.
|
||||
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
|
||||
more times for the following (max. 5 shown):
|
||||
TxD2
|
||||
To see the details of these warning messages, please use the -detail switch.
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:MapLib:564 - The following environment variables are currently set:
|
||||
INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1
|
||||
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
||||
rate limited output drivers. The delay on speed critical single ended outputs
|
||||
can be dramatically reduced by designating them as fast outputs.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
2 block(s) optimized away
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND XST_GND
|
||||
VCC XST_VCC
|
||||
|
||||
To enable printing of redundant blocks removed and signals merged, set the
|
||||
detailed map report option and rerun map.
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Strength | Rate | | | Delay |
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| RxD | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| TxD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
|
||||
| addr<0> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| addr<1> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| addr<2> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
|
||||
| irq_pin | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
|
||||
| led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
|
||||
| ncs | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| noe | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
|
||||
| nwe | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
|
||||
| reset | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
|
||||
| sram_data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Modular Design Summary
|
||||
-----------------------------------
|
||||
Modular Design not used for this design.
|
||||
|
||||
Section 11 - Timing Report
|
||||
--------------------------
|
||||
This design was not run using timing mode.
|
||||
|
||||
Section 12 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 13 - Control Set Information
|
||||
------------------------------------
|
||||
No control set information for this architecture.
|
||||
|
||||
Section 14 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| uart_peripheral/ | | 35/165 | 34/157 | 47/181 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | uart_peripheral |
|
||||
| +UART | | 0/130 | 0/123 | 0/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART |
|
||||
| ++buffrx1 | | 14/14 | 20/20 | 5/5 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/buffrx1 |
|
||||
| ++bufftx1 | | 12/12 | 17/17 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/bufftx1 |
|
||||
| ++ctrl_rx1 | | 3/3 | 5/5 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_rx1 |
|
||||
| ++ctrl_tx1 | | 6/6 | 6/6 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_tx1 |
|
||||
| ++dato_rdy1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/dato_rdy1 |
|
||||
| ++div161 | | 3/3 | 4/4 | 4/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div161 |
|
||||
| ++div27 | | 5/5 | 6/6 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div27 |
|
||||
| ++div_ms1 | | 31/31 | 33/33 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div_ms1 |
|
||||
| ++ier1 | | 3/3 | 3/3 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ier1 |
|
||||
| ++if_arm1 | | 18/18 | 0/0 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/if_arm1 |
|
||||
| ++ifrxd1 | | 1/1 | 2/2 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ifrxd1 |
|
||||
| ++isr1 | | 14/14 | 8/8 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/isr1 |
|
||||
| ++lcr1 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/lcr1 |
|
||||
| ++muestreo1 | | 7/7 | 6/6 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/muestreo1 |
|
||||
| ++pulso1 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso1 |
|
||||
| ++pulso2 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso2 |
|
||||
| ++pulso3 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso3 |
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Slices can be packed with basic elements from multiple hierarchies.
|
||||
Therefore, a slice will be counted in every hierarchical module
|
||||
that each of its packed basic elements belong to.
|
||||
** For each column, there are two numbers reported <A>/<B>.
|
||||
<A> is the number of elements that belong to that specific hierarchical module.
|
||||
<B> is the total number of elements from that hierarchical module and any lower level
|
||||
hierarchical modules below.
|
||||
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
|
||||
File diff suppressed because one or more lines are too long
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Reference in New Issue