mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Adding PS2, capacitive keyboard examples
This commit is contained in:
17
UART/logic/build/xst/work/hdllib.ref
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17
UART/logic/build/xst/work/hdllib.ref
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MO UART NULL ../uart.v vlg48/_u_a_r_t.bin 1289504228
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MO pc_bufftx NULL ../uart.v vlg1D/pc__bufftx.bin 1289504228
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MO pc_ctrl_tx_pc NULL ../uart.v vlg78/pc__ctrl__tx__pc.bin 1289504228
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MO pc_ifrxd NULL ../uart.v vlg5B/pc__ifrxd.bin 1289504228
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MO pc_ier NULL ../uart.v vlg72/pc__ier.bin 1289504228
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MO pc_muestreo NULL ../uart.v vlg1E/pc__muestreo.bin 1289504228
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MO pc_dato_rdy NULL ../uart.v vlg70/pc__dato__rdy.bin 1289504228
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MO pc_ctrl_rx NULL ../uart.v vlg6C/pc__ctrl__rx.bin 1289504228
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MO pc_div16 NULL ../uart.v vlg70/pc__div16.bin 1289504228
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MO pc_div27 NULL ../uart.v vlg76/pc__div27.bin 1289504228
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MO uart_peripheral NULL ../uart_peripheral.v vlg1B/uart__peripheral.bin 1289504228
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MO pc_lcr NULL ../uart.v vlg33/pc__lcr.bin 1289504228
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MO pc_isr NULL ../uart.v vlg38/pc__isr.bin 1289504228
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MO pc_buffrx_pc NULL ../uart.v vlg21/pc__buffrx__pc.bin 1289504228
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MO pc_div_ms NULL ../uart.v vlg34/pc__div__ms.bin 1289504228
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MO pc_if_arm_pc NULL ../uart.v vlg7E/pc__if__arm__pc.bin 1289504228
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MO pc_pulso NULL ../uart.v vlg21/pc__pulso.bin 1289504228
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BIN
UART/logic/build/xst/work/vlg1B/uart__peripheral.bin
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BIN
UART/logic/build/xst/work/vlg1B/uart__peripheral.bin
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BIN
UART/logic/build/xst/work/vlg1D/pc__bufftx.bin
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BIN
UART/logic/build/xst/work/vlg1D/pc__bufftx.bin
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BIN
UART/logic/build/xst/work/vlg1E/pc__muestreo.bin
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BIN
UART/logic/build/xst/work/vlg1E/pc__muestreo.bin
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BIN
UART/logic/build/xst/work/vlg21/pc__buffrx__pc.bin
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BIN
UART/logic/build/xst/work/vlg21/pc__buffrx__pc.bin
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BIN
UART/logic/build/xst/work/vlg21/pc__pulso.bin
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BIN
UART/logic/build/xst/work/vlg21/pc__pulso.bin
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BIN
UART/logic/build/xst/work/vlg33/pc__lcr.bin
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BIN
UART/logic/build/xst/work/vlg33/pc__lcr.bin
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BIN
UART/logic/build/xst/work/vlg34/pc__div__ms.bin
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BIN
UART/logic/build/xst/work/vlg34/pc__div__ms.bin
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BIN
UART/logic/build/xst/work/vlg38/pc__isr.bin
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BIN
UART/logic/build/xst/work/vlg38/pc__isr.bin
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BIN
UART/logic/build/xst/work/vlg48/_u_a_r_t.bin
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BIN
UART/logic/build/xst/work/vlg48/_u_a_r_t.bin
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BIN
UART/logic/build/xst/work/vlg5B/pc__ifrxd.bin
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BIN
UART/logic/build/xst/work/vlg5B/pc__ifrxd.bin
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BIN
UART/logic/build/xst/work/vlg6C/pc__ctrl__rx.bin
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BIN
UART/logic/build/xst/work/vlg6C/pc__ctrl__rx.bin
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BIN
UART/logic/build/xst/work/vlg70/pc__dato__rdy.bin
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BIN
UART/logic/build/xst/work/vlg70/pc__dato__rdy.bin
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BIN
UART/logic/build/xst/work/vlg70/pc__div16.bin
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BIN
UART/logic/build/xst/work/vlg70/pc__div16.bin
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BIN
UART/logic/build/xst/work/vlg72/pc__ier.bin
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BIN
UART/logic/build/xst/work/vlg72/pc__ier.bin
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BIN
UART/logic/build/xst/work/vlg76/pc__div27.bin
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BIN
UART/logic/build/xst/work/vlg76/pc__div27.bin
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BIN
UART/logic/build/xst/work/vlg78/pc__ctrl__tx__pc.bin
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BIN
UART/logic/build/xst/work/vlg78/pc__ctrl__tx__pc.bin
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BIN
UART/logic/build/xst/work/vlg7E/pc__if__arm__pc.bin
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BIN
UART/logic/build/xst/work/vlg7E/pc__if__arm__pc.bin
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