Adding PS2, capacitive keyboard examples

2025-04-21 12:27:27 +03:00 · 2010-11-30 19:26:56 -05:00
parent 2efe106cf3
commit 62d0edf217
275 changed files with 1696660 additions and 23991 deletions
--- a/cap_keyboard/logic/UART/Makefile
+++ b/cap_keyboard/logic/UART/Makefile
@@ -0,0 +1,88 @@
+DESIGN          = uart_peripheral
+PINS            = $(DESIGN).ucf
+DEVICE          = xc3s500e-VQ100-4
+BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
+                  -g CRC:enable -g StartUpClk:CCLK
+
+SIM_CMD         = vsim 
+SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
+SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
+IVERILOG        = iverilog
+
+SAKC_IP         = 192.168.254.101
+
+SRC             = uart_peripheral.v \
+		  uart.v
+
+SIM_SRC =uart_peripheral.v\
+
+ 
+all:            bits
+
+remake:         clean-build all
+
+clean:
+	rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat 
+	rm -rf *.bit build
+
+cleanall: clean
+	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
+
+bits:           $(DESIGN).bit
+
+#
+# Synthesis
+#
+build/project.src:
+	@[ -d build ] || mkdir build
+	@rm -f $@
+	for i in $(SRC); do echo verilog work ../$$i >> $@; done
+	for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
+
+build/project.xst: build/project.src
+	echo "run" > $@
+	echo "-top $(DESIGN) " >> $@
+	echo "-p $(DEVICE)" >> $@
+	echo "-opt_mode Area" >> $@
+	echo "-opt_level 1" >> $@
+	echo "-ifn project.src" >> $@
+	echo "-ifmt mixed" >> $@
+	echo "-ofn project.ngc" >> $@
+	echo "-ofmt NGC" >> $@
+	echo "-rtlview yes" >> $@
+
+build/project.ngc: build/project.xst $(SRC)
+	cd build && xst -ifn project.xst -ofn project.log
+
+build/project.ngd: build/project.ngc $(PINS)
+	cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
+
+build/project.ncd: build/project.ngd
+	cd build && map -pr b -p $(DEVICE) project
+
+build/project_r.ncd: build/project.ncd
+	cd build && par -w project project_r.ncd
+
+build/project_r.twr: build/project_r.ncd
+	cd build && trce -v 25 project_r.ncd project.pcf
+
+$(DESIGN).bit:  build/project_r.ncd build/project_r.twr
+	cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
+	@mv -f build/project_r.bit $@
+
+build/project_r.v: build/project_r.ncd
+	cd build &&  ngd2ver project.ngd  -w project.v
+
+modelsim: 
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
+
+timesim: build/project_r.v
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
+
+iversim:
+	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
+	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
+	gtkwave simulation/$(DESIGN)_TB.vcd&
+
+upload: $(DESIGN).bit
+	scp $(DESIGN).bit root@$(SAKC_IP):binaries 
--- a/cap_keyboard/logic/UART/uart.v
+++ b/cap_keyboard/logic/UART/uart.v
--- a/cap_keyboard/logic/UART/uart_peripheral.ucf
+++ b/cap_keyboard/logic/UART/uart_peripheral.ucf
@@ -0,0 +1,35 @@
+NET clk     LOC = "P38";
+NET reset   LOC = "P30";
+NET led     LOC = "P44";
+NET TxD		LOC = "p67";#To MAX-232
+NET RxD		LOC = "P70";
+NET irq_pin LOC = "P71";
+
+#ADDRESS BUS
+
+NET "addr<2>" LOC = "P79";
+NET "addr<1>" LOC = "P83";
+NET "addr<0>" LOC = "P84";
+
+#DATA BUS
+NET "sram_data<7>"  LOC = "P4";
+NET "sram_data<6>"  LOC = "P5";
+NET "sram_data<5>"  LOC = "P9";
+NET "sram_data<4>"  LOC = "P10";
+NET "sram_data<3>"  LOC = "P11";
+NET "sram_data<2>"  LOC = "P12";
+NET "sram_data<1>"  LOC = "P15";
+NET "sram_data<0>"  LOC = "P16";
+
+#CONTROL BUS
+NET "nwe"   LOC = "P88";
+NET "noe"   LOC = "P86";
+NET "ncs"   LOC = "P69";
+
+#ADC
+#NET "ADC_EOC"    LOC = "P17";
+#NET "ADC_SCLK"   LOC = "P18";
+#NET "ADC_SDIN"   LOC = "P22";
+#NET "ADC_SDOUT"  LOC = "P23";
+#NET "ADC_CS"     LOC = "P24";
+#NET "ADC_CSTART" LOC = "P26";
--- a/cap_keyboard/logic/UART/uart_peripheral.v
+++ b/cap_keyboard/logic/UART/uart_peripheral.v
@@ -0,0 +1,87 @@
+`timescale 1ns / 1ps
+module uart_peripheral(clk, sram_data, addr, nwe, ncs, noe, reset, led, RxD,TxD,irq_pin);
+  parameter     B = (7);
+
+  input            clk, nwe, ncs, noe, reset,RxD;
+  input [2:0]     addr;
+  inout [B:0]      sram_data;
+  output           led,TxD;
+  output            irq_pin;
+
+  // synchronize signals                               
+  reg    sncs, snwe;
+  reg    [2:0] buffer_addr;
+  reg    [B:0] buffer_data;  
+  reg [24:0]  counter;  
+  // interfaz fpga signals
+//  wire   [12:0] addr;
+	
+  // bram interfaz signals
+  reg    we;
+  reg    w_st;
+  wire [7:0] RD;
+  reg    [B:0] wdBus;
+  wire   [B:0] rdBus;
+
+  // interefaz signals assignments
+  wire   T = ~noe | ncs;
+  assign sram_data = T?8'bZ:rdBus;
+	
+  //--------------------------------------------------------------------------
+
+  // synchronize assignment
+  always  @(negedge clk)
+  begin
+    sncs   <= ncs;
+    snwe   <= nwe;
+    buffer_data <= sram_data;
+    buffer_addr <= addr;
+  end
+
+  // write access cpu to bram
+  always @(posedge clk)
+    if(~reset) {w_st, we, wdBus} <= 0;
+      else begin
+        wdBus <= buffer_data;
+        case (w_st)
+          0: begin
+              we <= 0;
+              if(sncs | snwe) w_st <= 1;
+          end
+          1: begin
+            if(~(sncs | snwe)) begin
+              we    <= 1;
+              w_st  <= 0;
+            end	
+            else we <= 0;
+          end
+        endcase
+      end
+
+
+
+//the UART Module
+UART UART(
+        .CLK(clk),
+        .reset(~reset),
+        .CS(~sncs),
+        .nRW(we),
+        .data_in(wdBus),
+        .data_out(rdBus),
+        .RxD(RxD),
+        .TxD(TxD),
+        .add(buffer_addr),
+		  .nIRQ(irq_pin)
+);
+
+ 
+  always @(posedge clk) begin
+    if (~reset)
+      counter <= {25{1'b0}};
+    else
+      counter <= counter + 1;
+  end 
+  assign led = counter[24];
+
+
+endmodule