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Adding ADC software example

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This commit is contained in:
Juan64Bits
2010-04-02 23:30:52 -05:00
parent 4d27db9265
commit 68b6b9a51f
10 changed files with 582 additions and 49 deletions
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79
Examples/ADC/logic/ADC.v
View File

@@ -16,30 +16,27 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
// synchronize signals
reg sncs, snwe;
reg [10:0] buffer_addr;
wire [8:0] addr2;
reg [B:0] buffer_data;
// interfaz fpga signals
wire [10:0] addr;
// bram interfaz signals
reg we;
wire we2;
reg w_st=0;
reg [B:0] wrBus;
wire [B:0] rdBus;
wire [B:0] wrBus2;
wire [B:0] rdBus2;
// interfaz fpga signals
wire [10:0] addr;
reg [25:0] counter;
// Test : LED blinking
always @(posedge clk) begin
if (reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;
led <=counter[25];
if (reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;
led <=counter[25];
end
// interefaz signals assignments
@@ -49,10 +46,10 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
// synchronize assignment
always @(negedge clk)
begin
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
end
// write access cpu to bram
@@ -75,30 +72,34 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
endcase
end
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(we), // Port A Write Enable Input
.WEB(we2) ); // Port B Write Enable Input
// Peripherals control
wire [3:0] csN;
wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000:
4'b0100)
: (buffer_addr[9]? 4'b0010:
4'b0001);
assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3:
rdBus2)
: (buffer_addr[9]? rdBus1:
rdBus0);
// Peripheral instantiation
ADC_peripheral P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
rdBus2, wrBus2, addr2);
ADC_peripheral P1(
.clk(clk),
.reset(reset),
.cs(csN[0]),
.ADC_EOC(ADC_EOC),
.ADC_CS(ADC_CS),
.ADC_CSTART(ADC_CSTART),
.ADC_SCLK(ADC_SCLK),
.ADC_SDIN(ADC_SDIN),
.ADC_SDOUT(ADC_SDOUT),
.addr(buffer_addr[8:0]),
.rdBus(rdBus0),
.wrBus(wrBus),
.we(we));
endmodule

47
Examples/ADC/logic/ADC_peripheral.v
View File

@@ -1,18 +1,21 @@
`timescale 1ns / 1ps
module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
rdBus2, wrBus2, addr2);
module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT,
addr, rdBus, wrBus, we);
input clk, reset, ADC_EOC;
input [7:0] rdBus2;
output we2, ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] wrBus2;
output [8:0] addr2;
input clk, reset, ADC_EOC, cs, we;
input [8:0] addr;
input [7:0] wrBus;
output ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] rdBus;
inout ADC_SDIN, ADC_SDOUT;
reg we2=0, nSample=0;
wire [7:0] rdBus2;
reg [7:0] wrBus2;
reg [8:0] addr2;
wire we1;
reg we2=0, nSample=0;
reg [7:0] auto_count=0;
reg [4:0] w_st2=0;
reg [3:0] SPI_in_data=0;
@@ -22,8 +25,31 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
reg [7:0] buffer_rd1;
reg [3:0] ADC_cmd;
assign we1 = we & cs;
assign ADC_CSTART = 1'b1;
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(addr[8:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(we1), // Port A Write Enable Input
.WEB(we2) ); // Port B Write Enable Input
// SPI comunication module instantiation
reg ADC_SCLK_buffer = 0;
reg ADC_SDIN_buffer = 0;
@@ -157,5 +183,6 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
//Sent clock divider for speed on SPI comunication
10: begin clkdiv = rdBus2; w_st2 <= 0; end
endcase
end
end
endmodule