qi-hardware/nn-usb-fpga
1
0
Fork 0
mirror of git://projects.qi-hardware.com/nn-usb-fpga.git synced 2025-04-21 12:27:27 +03:00
Code Activity

Adding ADC software example

Browse Source
This commit is contained in:
Juan64Bits
2010-04-02 23:30:52 -05:00
parent 4d27db9265
commit 68b6b9a51f
10 changed files with 582 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
Examples/ADC/logic/ADC_peripheral.v
View File

@@ -1,18 +1,21 @@
`timescale 1ns / 1ps
module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
rdBus2, wrBus2, addr2);
module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT,
addr, rdBus, wrBus, we);
input clk, reset, ADC_EOC;
input [7:0] rdBus2;
output we2, ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] wrBus2;
output [8:0] addr2;
input clk, reset, ADC_EOC, cs, we;
input [8:0] addr;
input [7:0] wrBus;
output ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] rdBus;
inout ADC_SDIN, ADC_SDOUT;
reg we2=0, nSample=0;
wire [7:0] rdBus2;
reg [7:0] wrBus2;
reg [8:0] addr2;
wire we1;
reg we2=0, nSample=0;
reg [7:0] auto_count=0;
reg [4:0] w_st2=0;
reg [3:0] SPI_in_data=0;
@@ -22,8 +25,31 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
reg [7:0] buffer_rd1;
reg [3:0] ADC_cmd;
assign we1 = we & cs;
assign ADC_CSTART = 1'b1;
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(addr[8:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(we1), // Port A Write Enable Input
.WEB(we2) ); // Port B Write Enable Input
// SPI comunication module instantiation
reg ADC_SCLK_buffer = 0;
reg ADC_SDIN_buffer = 0;
@@ -157,5 +183,6 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
//Sent clock divider for speed on SPI comunication
10: begin clkdiv = rdBus2; w_st2 <= 0; end
endcase
end
end
endmodule