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Code

Change ADC from Texas to Microchip MCP3008.

Browse Source 
Adding mcp3008 component
Adding SPI seerial flash X25X64MB.
Adding hierarchical label SRAM_CS, we want to use a serial SRAM for FPGA.
This commit is contained in:
carlos 2010-10-05 06:49:18 -05:00
parent d9b9e52111
commit 70a1465215
20 changed files with 479 additions and 383 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
KICAD_design_files/SAKC_PCB_v2/CONNECTORS.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/CONNECTORS.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/CPU.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 3 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/CPU.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 3 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

312
KICAD_design_files/SAKC_PCB_v2/D_CONVERTER.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 5 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -42,128 +43,204 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text HLabel 6600 2900 1 20 BiDi ~ 0
GND
Text HLabel 6000 2600 2 20 BiDi ~ 0
ANALOG[0..7]
Text HLabel 6480 3960 0 30 BiDi ~ 0
SRAM_CS
Text Label 9400 3750 0 40 ~ 0
D_GND
Wire Wire Line
9350 3750 9650 3750
Wire Wire Line
9650 3750 9650 3700
Connection ~ 6660 1640
Wire Wire Line
6900 1640 6660 1640
Wire Wire Line
6660 1640 6640 1640
Wire Wire Line
6660 1840 6900 1840
Wire Bus Line
6000 2600 5950 2600
9050 1740 9050 1840
Wire Bus Line
5950 2600 5950 2200
Wire Wire Line
5850 2400 5400 2400
Wire Wire Line
5850 2300 5400 2300
Wire Wire Line
5850 2200 5400 2200
Wire Wire Line
5850 2100 5400 2100
Connection ~ 5600 2700
Wire Wire Line
5600 2700 5700 2700
Wire Wire Line
6600 2900 6600 2800
Wire Wire Line
6600 2800 6550 2800
Connection ~ 5600 2800
Connection ~ 4250 2100
Wire Wire Line
4250 2050 4250 2150
Wire Wire Line
4400 2300 4250 2300
Wire Wire Line
4400 2400 4250 2400
Wire Wire Line
4400 2600 4250 2600
Wire Wire Line
5600 2550 5600 2600
Wire Wire Line
5600 2600 5400 2600
Wire Wire Line
5400 2650 5600 2650
Wire Wire Line
5600 2650 5600 2950
Wire Wire Line
5600 2950 4900 2950
Wire Wire Line
4400 2650 4250 2650
Wire Wire Line
4400 2450 4250 2450
Wire Wire Line
4400 2350 4250 2350
Wire Wire Line
4250 2150 4400 2150
Wire Wire Line
4400 2100 4250 2100
Wire Wire Line
4900 1900 4900 1850
9050 1840 9050 1940
Wire Bus Line
9050 1940 9050 2040
Wire Bus Line
9050 2040 9050 2140
Wire Bus Line
9050 2140 9050 2240
Wire Bus Line
9050 2240 9050 2340
Wire Bus Line
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Wire Wire Line
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Wire Wire Line
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6900 2240 6540 2240
Wire Wire Line
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6900 2040 6540 2040
Wire Wire Line
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6900 2140 6540 2140
Wire Wire Line
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Entry Wire Line
5850 2450 5950 2550
Entry Wire Line
5850 2400 5950 2500
Entry Wire Line
5850 2350 5950 2450
Entry Wire Line
5850 2300 5950 2400
Entry Wire Line
5850 2250 5950 2350
Entry Wire Line
5850 2200 5950 2300
Entry Wire Line
5850 2150 5950 2250
Entry Wire Line
5850 2100 5950 2200
Text Label 5600 2450 2 20 ~ 0
ANALOG7
Text Label 5600 2400 2 20 ~ 0
ANALOG6
Text Label 5600 2350 2 20 ~ 0
ANALOG5
Text Label 5600 2300 2 20 ~ 0
ANALOG4
Text Label 5600 2250 2 20 ~ 0
ANALOG3
Text Label 5600 2200 2 20 ~ 0
ANALOG2
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ANALOG1
Text Label 5600 2100 2 20 ~ 0
ANALOG0
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3.3V
Text GLabel 4900 1850 3 20 BiDi ~ 0
3.3V
Text GLabel 4250 2050 3 20 BiDi ~ 0
3.3V
Text GLabel 3750 2000 1 20 BiDi ~ 0
3.3V
Text HLabel 3750 1800 3 20 BiDi ~ 0
3.3V
Text HLabel 5700 2700 2 20 BiDi ~ 0
AN_GND
Text HLabel 4250 2300 0 20 BiDi ~ 0
ADC_EOC
Text HLabel 4250 2350 0 20 BiDi ~ 0
7000 2800 6550 2800
Wire Wire Line
7090 3610 6840 3610
Wire Wire Line
8790 3460 8890 3460
Wire Wire Line
6430 3410 7090 3410
Wire Wire Line
8790 3560 9190 3560
Wire Wire Line
8790 3660 9190 3660
Wire Wire Line
7090 3510 6420 3510
Wire Wire Line
8790 3360 8890 3360
Wire Wire Line
8890 3360 8990 3360
Wire Wire Line
6840 3710 7090 3710
Wire Wire Line
8890 3460 8890 3360
Connection ~ 8890 3360
Wire Bus Line
9050 2440 9100 2440
Wire Wire Line
8950 2240 8500 2240
Wire Wire Line
8950 2040 8500 2040
Wire Wire Line
8950 1840 8500 1840
Wire Wire Line
8950 1640 8500 1640
Wire Wire Line
8950 1740 8500 1740
Wire Wire Line
8950 1940 8500 1940
Wire Wire Line
8950 2140 8500 2140
Wire Wire Line
8950 2340 8500 2340
Wire Wire Line
6660 1640 6660 1740
Wire Wire Line
6660 1740 6900 1740
Wire Wire Line
6660 2340 6900 2340
Wire Wire Line
9400 3150 9650 3150
Wire Wire Line
9650 3150 9650 3300
Text GLabel 9450 3150 0 20 BiDi ~ 0
3V3
$Comp
L C C76
U 1 1 4CAB0DB2
P 9650 3500
F 0 "C76" H 9700 3600 50 0000 L CNN
F 1 "100n" H 9700 3400 50 0000 L CNN
1 9650 3500
1 0 0 1
$EndComp
Text HLabel 6430 3410 0 30 BiDi ~ 0
SFLASH_CS
Text Label 6560 2240 0 40 ~ 0
ADC_CS
Text HLabel 4250 2400 0 20 BiDi ~ 0
ADC_CSTART
Text HLabel 4250 2450 0 20 BiDi ~ 0
ADC_SCLK
Text HLabel 4250 2600 0 20 BiDi ~ 0
Text Label 6560 2140 0 40 ~ 0
ADC_SDIN
Text HLabel 4250 2650 0 20 BiDi ~ 0
Text Label 6560 2040 0 40 ~ 0
ADC_SDOUT
Text Label 6560 1940 0 40 ~ 0
ADC_SCLK
Text Label 6680 2340 0 40 ~ 0
D_GND
Text Label 6680 1840 0 40 ~ 0
A_GND
Text Label 6640 2800 0 40 ~ 0
D_GND
Text Label 5700 2800 0 40 ~ 0
A_GND
Text Label 8570 2340 0 40 ~ 0
ANALOG7
Text Label 8570 2240 0 40 ~ 0
ANALOG6
Text Label 8560 2140 0 40 ~ 0
ANALOG5
Text Label 8560 2040 0 40 ~ 0
ANALOG4
Text Label 8560 1940 0 40 ~ 0
ANALOG3
Text Label 8560 1840 0 40 ~ 0
ANALOG2
Text Label 8550 1740 0 40 ~ 0
ANALOG1
Text Label 8540 1640 0 40 ~ 0
ANALOG0
Entry Wire Line
8950 1640 9050 1740
Entry Wire Line
8950 1740 9050 1840
Entry Wire Line
8950 1840 9050 1940
Entry Wire Line
8950 1940 9050 2040
Entry Wire Line
8950 2040 9050 2140
Entry Wire Line
8950 2140 9050 2240
Entry Wire Line
8950 2240 9050 2340
Entry Wire Line
8950 2340 9050 2440
Text HLabel 9100 2440 2 30 BiDi ~ 0
ANALOG[0..7]
Text Label 9190 3660 2 40 ~ 0
ADC_SDIN
Text Label 6840 3410 2 40 ~ 0
SFLASH_CS
Text Label 6840 3510 2 40 ~ 0
ADC_SDOUT
$Comp
L X25X64MB U5
U 1 1 4CAA8B05
P 7940 3510
F 0 "U5" H 7940 3510 60 0000 C CNN
F 1 "X25X64MB" H 7940 3360 60 0000 C CNN
1 7940 3510
1 0 0 -1
$EndComp
Text GLabel 6840 3710 0 20 BiDi ~ 0
GND
Text GLabel 8990 3360 2 20 BiDi ~ 0
3V3
Text GLabel 6840 3610 0 20 BiDi ~ 0
3V3
Text Label 8910 3560 0 40 ~ 0
ADC_SCLK
$Comp
L MCP3008 U11
U 1 1 4CAA4935
P 7750 1940
F 0 "U11" H 7750 1940 60 0000 C CNN
F 1 "MCP3008" H 7750 1840 60 0000 C CNN
1 7750 1940
1 0 0 -1
$EndComp
Text HLabel 7000 2800 2 30 BiDi ~ 0
GND
Text GLabel 6640 1640 0 20 BiDi ~ 0
3.3V
Text HLabel 5600 2800 0 30 BiDi ~ 0
AN_GND
Text HLabel 6540 2240 0 30 BiDi ~ 0
ADC_CS
Text HLabel 6540 1940 0 30 BiDi ~ 0
ADC_SCLK
Text HLabel 6540 2140 0 30 BiDi ~ 0
ADC_SDIN
Text HLabel 6540 2040 0 30 BiDi ~ 0
ADC_SDOUT
$Comp
L INDUCTOR L12
@ -174,13 +251,4 @@ F 1 "HZ0805C202R-00" V 6350 2800 40 0000 C CNN
1 6250 2800
0 -1 -1 0
$EndComp
$Comp
L TLV1548 U11
U 1 1 4B7C620D
P 4700 2900
F 0 "U11" H 4550 3800 60 0000 C CNN
F 1 "TLV1548" H 4700 2900 40 0000 C CNN
1 4700 2900
1 0 0 -1
$EndComp
$EndSCHEMATC

312
KICAD_design_files/SAKC_PCB_v2/D_CONVERTER.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 5 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -42,128 +43,204 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text HLabel 6600 2900 1 20 BiDi ~ 0
GND
Text HLabel 6000 2600 2 20 BiDi ~ 0
ANALOG[0..7]
Text HLabel 6480 3960 0 30 BiDi ~ 0
SRAM_CS
Text Label 9400 3750 0 40 ~ 0
D_GND
Wire Wire Line
9350 3750 9650 3750
Wire Wire Line
9650 3750 9650 3700
Connection ~ 6660 1640
Wire Wire Line
6900 1640 6660 1640
Wire Wire Line
6660 1640 6640 1640
Wire Wire Line
6660 1840 6900 1840
Wire Bus Line
6000 2600 5950 2600
9050 1740 9050 1840
Wire Bus Line
5950 2600 5950 2200
Wire Wire Line
5850 2400 5400 2400
Wire Wire Line
5850 2300 5400 2300
Wire Wire Line
5850 2200 5400 2200
Wire Wire Line
5850 2100 5400 2100
Connection ~ 5600 2700
Wire Wire Line
5600 2700 5700 2700
Wire Wire Line
6600 2900 6600 2800
Wire Wire Line
6600 2800 6550 2800
Connection ~ 5600 2800
Connection ~ 4250 2100
Wire Wire Line
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Wire Wire Line
4400 2300 4250 2300
Wire Wire Line
4400 2400 4250 2400
Wire Wire Line
4400 2600 4250 2600
Wire Wire Line
5600 2550 5600 2600
Wire Wire Line
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Wire Wire Line
5400 2650 5600 2650
Wire Wire Line
5600 2650 5600 2950
Wire Wire Line
5600 2950 4900 2950
Wire Wire Line
4400 2650 4250 2650
Wire Wire Line
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Wire Wire Line
4400 2350 4250 2350
Wire Wire Line
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Wire Wire Line
4400 2100 4250 2100
Wire Wire Line
4900 1900 4900 1850
9050 1840 9050 1940
Wire Bus Line
9050 1940 9050 2040
Wire Bus Line
9050 2040 9050 2140
Wire Bus Line
9050 2140 9050 2240
Wire Bus Line
9050 2240 9050 2340
Wire Bus Line
9050 2340 9050 2440
Wire Wire Line
5950 2800 5600 2800
Wire Wire Line
3750 2000 3750 1800
6900 2240 6540 2240
Wire Wire Line
5850 2150 5400 2150
6900 1940 6540 1940
Wire Wire Line
5850 2250 5400 2250
6900 2040 6540 2040
Wire Wire Line
5850 2350 5400 2350
6900 2140 6540 2140
Wire Wire Line
5850 2450 5400 2450
Entry Wire Line
5850 2450 5950 2550
Entry Wire Line
5850 2400 5950 2500
Entry Wire Line
5850 2350 5950 2450
Entry Wire Line
5850 2300 5950 2400
Entry Wire Line
5850 2250 5950 2350
Entry Wire Line
5850 2200 5950 2300
Entry Wire Line
5850 2150 5950 2250
Entry Wire Line
5850 2100 5950 2200
Text Label 5600 2450 2 20 ~ 0
ANALOG7
Text Label 5600 2400 2 20 ~ 0
ANALOG6
Text Label 5600 2350 2 20 ~ 0
ANALOG5
Text Label 5600 2300 2 20 ~ 0
ANALOG4
Text Label 5600 2250 2 20 ~ 0
ANALOG3
Text Label 5600 2200 2 20 ~ 0
ANALOG2
Text Label 5600 2150 2 20 ~ 0
ANALOG1
Text Label 5600 2100 2 20 ~ 0
ANALOG0
Text GLabel 5600 2550 2 20 BiDi ~ 0
3.3V
Text GLabel 4900 1850 3 20 BiDi ~ 0
3.3V
Text GLabel 4250 2050 3 20 BiDi ~ 0
3.3V
Text GLabel 3750 2000 1 20 BiDi ~ 0
3.3V
Text HLabel 3750 1800 3 20 BiDi ~ 0
3.3V
Text HLabel 5700 2700 2 20 BiDi ~ 0
AN_GND
Text HLabel 4250 2300 0 20 BiDi ~ 0
ADC_EOC
Text HLabel 4250 2350 0 20 BiDi ~ 0
7000 2800 6550 2800
Wire Wire Line
7090 3610 6840 3610
Wire Wire Line
8790 3460 8890 3460
Wire Wire Line
6430 3410 7090 3410
Wire Wire Line
8790 3560 9190 3560
Wire Wire Line
8790 3660 9190 3660
Wire Wire Line
7090 3510 6420 3510
Wire Wire Line
8790 3360 8890 3360
Wire Wire Line
8890 3360 8990 3360
Wire Wire Line
6840 3710 7090 3710
Wire Wire Line
8890 3460 8890 3360
Connection ~ 8890 3360
Wire Bus Line
9050 2440 9100 2440
Wire Wire Line
8950 2240 8500 2240
Wire Wire Line
8950 2040 8500 2040
Wire Wire Line
8950 1840 8500 1840
Wire Wire Line
8950 1640 8500 1640
Wire Wire Line
8950 1740 8500 1740
Wire Wire Line
8950 1940 8500 1940
Wire Wire Line
8950 2140 8500 2140
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6660 2340 6900 2340
Wire Wire Line
9400 3150 9650 3150
Wire Wire Line
9650 3150 9650 3300
Text GLabel 9450 3150 0 20 BiDi ~ 0
3V3
$Comp
L C C76
U 1 1 4CAB0DB2
P 9650 3500
F 0 "C76" H 9700 3600 50 0000 L CNN
F 1 "100n" H 9700 3400 50 0000 L CNN
1 9650 3500
1 0 0 1
$EndComp
Text HLabel 6430 3410 0 30 BiDi ~ 0
SFLASH_CS
Text Label 6560 2240 0 40 ~ 0
ADC_CS
Text HLabel 4250 2400 0 20 BiDi ~ 0
ADC_CSTART
Text HLabel 4250 2450 0 20 BiDi ~ 0
ADC_SCLK
Text HLabel 4250 2600 0 20 BiDi ~ 0
Text Label 6560 2140 0 40 ~ 0
ADC_SDIN
Text HLabel 4250 2650 0 20 BiDi ~ 0
Text Label 6560 2040 0 40 ~ 0
ADC_SDOUT
Text Label 6560 1940 0 40 ~ 0
ADC_SCLK
Text Label 6680 2340 0 40 ~ 0
D_GND
Text Label 6680 1840 0 40 ~ 0
A_GND
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D_GND
Text Label 5700 2800 0 40 ~ 0
A_GND
Text Label 8570 2340 0 40 ~ 0
ANALOG7
Text Label 8570 2240 0 40 ~ 0
ANALOG6
Text Label 8560 2140 0 40 ~ 0
ANALOG5
Text Label 8560 2040 0 40 ~ 0
ANALOG4
Text Label 8560 1940 0 40 ~ 0
ANALOG3
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ANALOG2
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ANALOG1
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Text HLabel 9100 2440 2 30 BiDi ~ 0
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ADC_SDOUT
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L X25X64MB U5
U 1 1 4CAA8B05
P 7940 3510
F 0 "U5" H 7940 3510 60 0000 C CNN
F 1 "X25X64MB" H 7940 3360 60 0000 C CNN
1 7940 3510
1 0 0 -1
$EndComp
Text GLabel 6840 3710 0 20 BiDi ~ 0
GND
Text GLabel 8990 3360 2 20 BiDi ~ 0
3V3
Text GLabel 6840 3610 0 20 BiDi ~ 0
3V3
Text Label 8910 3560 0 40 ~ 0
ADC_SCLK
$Comp
L MCP3008 U11
U 1 1 4CAA4935
P 7750 1940
F 0 "U11" H 7750 1940 60 0000 C CNN
F 1 "MCP3008" H 7750 1840 60 0000 C CNN
1 7750 1940
1 0 0 -1
$EndComp
Text HLabel 7000 2800 2 30 BiDi ~ 0
GND
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3.3V
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AN_GND
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ADC_SCLK
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ADC_SDIN
Text HLabel 6540 2040 0 30 BiDi ~ 0
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$Comp
L INDUCTOR L12
@ -174,13 +251,4 @@ F 1 "HZ0805C202R-00" V 6350 2800 40 0000 C CNN
1 6250 2800
0 -1 -1 0
$EndComp
$Comp
L TLV1548 U11
U 1 1 4B7C620D
P 4700 2900
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1 4700 2900
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$EndComp
$EndSCHEMATC

29
KICAD_design_files/SAKC_PCB_v2/Design files/mcp3008.lib Normal file
View File

@ -0,0 +1,29 @@
EESchema-LIBRARY Version 2.3 Date: Mon 04 Oct 2010 04:36:09 PM COT
#
# MCP3008
#
DEF MCP3008 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MCP3008" 0 -100 60 H V C CNN
DRAW
S -550 400 450 -550 0 1 10 f
X CH0 1 750 300 300 L 50 50 1 1 B
X CH1 2 750 200 300 L 50 50 1 1 B
X CH2 3 750 100 300 L 50 50 1 1 B
X CH3 4 750 0 300 L 50 50 1 1 B
X CH4 5 750 -100 300 L 50 50 1 1 B
X CH5 6 750 -200 300 L 50 50 1 1 B
X CH6 7 750 -300 300 L 50 50 1 1 B
X CH7 8 750 -400 300 L 50 50 1 1 B
X DGND 9 -850 -400 300 R 50 50 1 1 B
X nCS/SHDN 10 -850 -300 300 R 50 50 1 1 B
X DIN 11 -850 -200 300 R 50 50 1 1 B
X DOUT 12 -850 -100 300 R 50 50 1 1 B
X CLK 13 -850 0 300 R 50 50 1 1 B
X AGND 14 -850 100 300 R 50 50 1 1 B
X VREF 15 -850 200 300 R 50 50 1 1 B
X VDD 16 -850 300 300 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

48
KICAD_design_files/SAKC_PCB_v2/FPGA.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 8 9
Title "noname.sch"
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -42,14 +43,6 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 10630 1890 0 40 ~ 0
ADC_SCLK
Wire Wire Line
8810 1940 8560 1940
Wire Wire Line
10510 1790 10610 1790
Wire Wire Line
8160 1740 8810 1740
Wire Wire Line
7850 2700 8000 2700
Connection ~ 4250 6350
@ -554,40 +547,6 @@ Wire Wire Line
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Wire Wire Line
7850 2650 8000 2650
Wire Wire Line
10510 1890 10910 1890
Wire Wire Line
10510 1990 10910 1990
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 10610 1690
Text GLabel 8560 1940 0 20 BiDi ~ 0
3V3
Text GLabel 10710 1690 2 20 BiDi ~ 0
3V3
Text GLabel 8560 2040 0 20 BiDi ~ 0
GND
$Comp
L X25X64MB U?
U 1 1 4CA77E38
P 9660 1840
F 0 "U?" H 9660 1840 60 0000 C CNN
F 1 "X25X64MB" H 9660 1690 60 0000 C CNN
1 9660 1840
1 0 0 -1
$EndComp
Text Label 8560 1840 2 40 ~ 0
ADC_SDOUT
Text Label 8560 1740 2 40 ~ 0
SFLASH_CS
Text Label 10910 1990 2 40 ~ 0
ADC_SDIN
Text Label 7900 2700 0 20 ~ 0
GPIO47
Text Label 7900 2650 0 20 ~ 0
@ -1093,7 +1052,6 @@ ADC_SCLK
Text HLabel 3250 2250 0 20 BiDi ~ 0
ADC_EOC
NoConn ~ 1650 2800
NoConn ~ 9400 4150
NoConn ~ 3250 2650
Text Label 3250 2650 0 20 ~ 0
GPIO17

48
KICAD_design_files/SAKC_PCB_v2/FPGA.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 8 9
Title "noname.sch"
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -42,14 +43,6 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 10630 1890 0 40 ~ 0
ADC_SCLK
Wire Wire Line
8810 1940 8560 1940
Wire Wire Line
10510 1790 10610 1790
Wire Wire Line
8160 1740 8810 1740
Wire Wire Line
7850 2700 8000 2700
Connection ~ 4250 6350
@ -554,40 +547,6 @@ Wire Wire Line
3250 2700 3500 2700
Wire Wire Line
7850 2650 8000 2650
Wire Wire Line
10510 1890 10910 1890
Wire Wire Line
10510 1990 10910 1990
Wire Wire Line
8810 1840 8160 1840
Wire Wire Line
10710 1690 10510 1690
Wire Wire Line
8560 2040 8810 2040
Wire Wire Line
10610 1790 10610 1690
Connection ~ 10610 1690
Text GLabel 8560 1940 0 20 BiDi ~ 0
3V3
Text GLabel 10710 1690 2 20 BiDi ~ 0
3V3
Text GLabel 8560 2040 0 20 BiDi ~ 0
GND
$Comp
L X25X64MB U?
U 1 1 4CA77E38
P 9660 1840
F 0 "U?" H 9660 1840 60 0000 C CNN
F 1 "X25X64MB" H 9660 1690 60 0000 C CNN
1 9660 1840
1 0 0 -1
$EndComp
Text Label 8560 1840 2 40 ~ 0
ADC_SDOUT
Text Label 8560 1740 2 40 ~ 0
SFLASH_CS
Text Label 10910 1990 2 40 ~ 0
ADC_SDIN
Text Label 7900 2700 0 20 ~ 0
GPIO47
Text Label 7900 2650 0 20 ~ 0
@ -1093,7 +1052,6 @@ ADC_SCLK
Text HLabel 3250 2250 0 20 BiDi ~ 0
ADC_EOC
NoConn ~ 1650 2800
NoConn ~ 9400 4150
NoConn ~ 3250 2650
Text Label 3250 2650 0 20 ~ 0
GPIO17

5
KICAD_design_files/SAKC_PCB_v2/LCD.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 9 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/LCD.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 9 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/MEMORY.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 6 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/MEMORY.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 6 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/POWER_SUPPLY.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 2 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/POWER_SUPPLY.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 2 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

25
KICAD_design_files/SAKC_PCB_v2/SAKC.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 1 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -302,20 +303,20 @@ F11 "RXDF" B R 7030 3570 20
F12 "TXDF" B R 7030 3540 20
$EndSheet
$Sheet
S 2050 2580 500 270
S 2050 2580 500 320
U 4B8F5F86
F0 "AD_CONVERTER" 20
F1 "D_CONVERTER.sch" 20
F2 "ANALOG[0..7]" B R 2550 2820 20
F3 "3.3V" B L 2050 2820 20
F3 "3.3V" B L 2050 2840 20
F4 "AN_GND" B R 2550 2780 20
F5 "ADC_EOC" B R 2550 2750 20
F6 "ADC_CS" B R 2550 2630 20
F7 "ADC_CSTART" B R 2550 2600 20
F8 "ADC_SCLK" B R 2550 2720 20
F9 "ADC_SDIN" B R 2550 2690 20
F10 "ADC_SDOUT" B R 2550 2660 20
F11 "GND" B L 2050 2790 20
F5 "ADC_CS" B R 2550 2630 20
F6 "ADC_SCLK" B R 2550 2720 20
F7 "ADC_SDIN" B R 2550 2690 20
F8 "ADC_SDOUT" B R 2550 2660 20
F9 "GND" B L 2050 2790 20
F10 "SFLASH_CS" B R 2550 2600 20
F11 "SRAM_CS" B R 2550 2750 20
$EndSheet
$Sheet
S 6530 2610 500 670
@ -452,7 +453,7 @@ Text GLabel 7030 3660 2 20 BiDi ~ 0
3.3V
Text GLabel 2550 2780 2 20 BiDi ~ 0
AN_GND
Text GLabel 2050 2820 0 20 BiDi ~ 0
Text GLabel 2050 2840 0 20 BiDi ~ 0
3.3V
Text GLabel 7030 3240 2 20 BiDi ~ 0
3.3V

3
KICAD_design_files/SAKC_PCB_v2/SAKC.pro
View File

@ -1,4 +1,4 @@
update=Sat 02 Oct 2010 01:50:50 PM COT
update=Mon 04 Oct 2010 04:37:43 PM COT
last_client=eeschema
[general]
version=1
@ -285,4 +285,5 @@ LibName26=siliconi
LibName27=contrib
LibName28=valves
LibName29=Design files/x25x64mb
LibName30=Design files/mcp3008

25
KICAD_design_files/SAKC_PCB_v2/SAKC.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 1 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -302,20 +303,20 @@ F11 "RXDF" B R 7030 3570 20
F12 "TXDF" B R 7030 3540 20
$EndSheet
$Sheet
S 2050 2580 500 270
S 2050 2580 500 320
U 4B8F5F86
F0 "AD_CONVERTER" 20
F1 "D_CONVERTER.sch" 20
F2 "ANALOG[0..7]" B R 2550 2820 20
F3 "3.3V" B L 2050 2820 20
F3 "3.3V" B L 2050 2840 20
F4 "AN_GND" B R 2550 2780 20
F5 "ADC_EOC" B R 2550 2750 20
F6 "ADC_CS" B R 2550 2630 20
F7 "ADC_CSTART" B R 2550 2600 20
F8 "ADC_SCLK" B R 2550 2720 20
F9 "ADC_SDIN" B R 2550 2690 20
F10 "ADC_SDOUT" B R 2550 2660 20
F11 "GND" B L 2050 2790 20
F5 "ADC_CS" B R 2550 2630 20
F6 "ADC_SCLK" B R 2550 2720 20
F7 "ADC_SDIN" B R 2550 2690 20
F8 "ADC_SDOUT" B R 2550 2660 20
F9 "GND" B L 2050 2790 20
F10 "SFLASH_CS" B R 2550 2600 20
F11 "SRAM_CS" B R 2550 2750 20
$EndSheet
$Sheet
S 6530 2610 500 670
@ -452,7 +453,7 @@ Text GLabel 7030 3660 2 20 BiDi ~ 0
3.3V
Text GLabel 2550 2780 2 20 BiDi ~ 0
AN_GND
Text GLabel 2050 2820 0 20 BiDi ~ 0
Text GLabel 2050 2840 0 20 BiDi ~ 0
3.3V
Text GLabel 7030 3240 2 20 BiDi ~ 0
3.3V

5
KICAD_design_files/SAKC_PCB_v2/UART_USB_I2C.bak
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:05:26 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:07 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""

5
KICAD_design_files/SAKC_PCB_v2/UART_USB_I2C.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat 02 Oct 2010 02:18:00 PM COT
EESchema Schematic File Version 2 date Tue 05 Oct 2010 06:46:32 AM COT
LIBS:power
LIBS:header_40
LIBS:device
@ -28,13 +28,14 @@ LIBS:siliconi
LIBS:contrib
LIBS:valves
LIBS:x25x64mb
LIBS:mcp3008
LIBS:SAKC-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "2 oct 2010"
Date "5 oct 2010"
Rev ""
Comp ""
Comment1 ""