diff --git a/Examples/blink/logic/Makefile b/Examples/blink/logic/Makefile index 0cfa99f..a3adbe5 100644 --- a/Examples/blink/logic/Makefile +++ b/Examples/blink/logic/Makefile @@ -16,7 +16,7 @@ all: bits remake: clean-build all clean: - rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat + rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat rm -f *.bit cleanall: clean @@ -63,8 +63,15 @@ build/project_r.twr: build/project_r.ncd $(DESIGN).bit: build/project_r.ncd build/project_r.twr cd build && bitgen project_r.ncd -l -w $(BGFLAGS) @mv -f build/project_r.bit $@ + +build/project_r.v: build/project_r.ncd + cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v + sim: - cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do + cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do + +timesim: build/project_r.v + cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do upload: $(DESIGN).bit scp $(DESIGN).bit root@$(SAKC_IP): diff --git a/Examples/blink/logic/simulation/blink_TB.do b/Examples/blink/logic/simulation/blink_TB.do index 2441533..01f7deb 100644 --- a/Examples/blink/logic/simulation/blink_TB.do +++ b/Examples/blink/logic/simulation/blink_TB.do @@ -1,11 +1,13 @@ vlib work -vlog +acc "../blink.v" -vlog +acc "../blink_TB.v" -vlog +acc "glbl.v" -vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver blink_TB_v glbl +vlog -incr +libext+.v \ + "../blink.v" \ + "../blink_TB.v" \ + "glbl.v" + +vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl view wave -do wave.do -#add wave * +#do wave.do +add wave * add wave /glbl/GSR view structure view signals diff --git a/Examples/blink/logic/simulation/blink_TIMING_TB.do b/Examples/blink/logic/simulation/blink_TIMING_TB.do new file mode 100644 index 0000000..72061bd --- /dev/null +++ b/Examples/blink/logic/simulation/blink_TIMING_TB.do @@ -0,0 +1,10 @@ +vlib work +vlog -incr "../build/project.v" "../blink_TB.v" "glbl.v" +vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl +view wave +#do wave.do +add wave * +add wave /glbl/GSR +view structure +view signals +run 15ms diff --git a/Examples/sram/logic/Makefile b/Examples/sram/logic/Makefile index 9f3a495..056bb8f 100644 --- a/Examples/sram/logic/Makefile +++ b/Examples/sram/logic/Makefile @@ -6,7 +6,6 @@ BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ SIM_CMD = /opt/cad/modeltech/bin/vsim SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do -#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) SAKC_IP = 192.168.254.101 @@ -67,8 +66,15 @@ build/project_r.twr: build/project_r.ncd $(DESIGN).bit: build/project_r.ncd build/project_r.twr cd build && bitgen project_r.ncd -l -w $(BGFLAGS) @mv -f build/project_r.bit $@ + +build/project_r.v: build/project_r.ncd + cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v + sim: - cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do + cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do + +timesim: build/project_r.v + cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do upload: $(DESIGN).bit scp $(DESIGN).bit root@$(SAKC_IP): diff --git a/Examples/sram/logic/simulation/glbl.v b/Examples/sram/logic/simulation/glbl.v new file mode 100644 index 0000000..c9280c6 --- /dev/null +++ b/Examples/sram/logic/simulation/glbl.v @@ -0,0 +1,58 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $ + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire PRLD; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule diff --git a/Examples/sram/logic/simulation/sram_bus_TB.do b/Examples/sram/logic/simulation/sram_bus_TB.do new file mode 100644 index 0000000..1c045a7 --- /dev/null +++ b/Examples/sram/logic/simulation/sram_bus_TB.do @@ -0,0 +1,12 @@ +vlib work +vlog -incr +libext+.v \ + "../sram_bus.v" \ + "../sram_bus_TB.v" \ + "glbl.v" +vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl +view wave +#do wave.do +add wave * +view structure +view signals +run 5us diff --git a/Examples/sram/logic/simulation/sram_bus_TIMING_TB.do b/Examples/sram/logic/simulation/sram_bus_TIMING_TB.do new file mode 100644 index 0000000..ab6f8a6 --- /dev/null +++ b/Examples/sram/logic/simulation/sram_bus_TIMING_TB.do @@ -0,0 +1,9 @@ +vlib work +vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v" +vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl +view wave +#do wave.do +add wave * +view structure +view signals +run 5us diff --git a/Examples/sram/logic/simulation/transcript b/Examples/sram/logic/simulation/transcript new file mode 100644 index 0000000..653e976 --- /dev/null +++ b/Examples/sram/logic/simulation/transcript @@ -0,0 +1,63 @@ +# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic +# // +# // Copyright Mentor Graphics Corporation 2005 +# // All Rights Reserved. +# // +# // THIS WORK CONTAINS TRADE SECRET AND +# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY +# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS +# // AND IS SUBJECT TO LICENSE TERMS. +# // +# do sram_bus_TIMING_TB.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005 +# -- Compiling module sram_bus +# -- Compiling module glbl +# -- Compiling module sram_bus_TB_v +# ** Warning: glbl.v(5): 'glbl' already exists. +# -- Compiling module glbl +# +# Top level modules: +# glbl +# sram_bus_TB_v +# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl +# Loading work.sram_bus_TB_v +# Loading work.sram_bus +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV +# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF +# Loading work.glbl +# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7. +# Region: /sram_bus_TB_v/uut +# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'. +# Region: /sram_bus_TB_v/uut +# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'. +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4 +# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4 +# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs +# .main_pane.workspace +# .main_pane.signals.interior.cs + + + + + +exit diff --git a/Examples/sram/logic/simulation/vsim.wlf b/Examples/sram/logic/simulation/vsim.wlf new file mode 100644 index 0000000..231dff4 Binary files /dev/null and b/Examples/sram/logic/simulation/vsim.wlf differ diff --git a/Examples/sram/logic/simulation/wave.do b/Examples/sram/logic/simulation/wave.do new file mode 100644 index 0000000..9ad4110 --- /dev/null +++ b/Examples/sram/logic/simulation/wave.do @@ -0,0 +1,29 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/clk +add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/addr +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/nwe +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/ncs +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/noe +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/reset +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/led +add wave -noupdate -format Literal -radix hexadecimal {/sram_bus_TB_v/sram_data$inout$reg} +add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/sram_data +add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/data_tx +add wave -noupdate -format Logic -radix hexadecimal /glbl/GSR +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {154070 ps} 0} +configure wave -namecolwidth 323 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {656250 ps} diff --git a/Examples/sram/logic/simulation/work/_info b/Examples/sram/logic/simulation/work/_info new file mode 100644 index 0000000..e107c86 --- /dev/null +++ b/Examples/sram/logic/simulation/work/_info @@ -0,0 +1,32 @@ +m255 +13 +cModel Technology +d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation +vglbl +IT?5S;>bN`@zG_25]R_4A33 +VnN]4Gon>inod6>M^M2[SV1 +w1273510321 +Fglbl.v +L0 5 +OE;L;6.0d;29 +r1 +31 +vsram_bus +IYS7oKaz71LdIhQ>[[g2fo3 +V7bnNHP1kz?3UaZfjPj4WE1 +w1273511584 +F../build/project.v +L0 37 +OE;L;6.0d;29 +r1 +31 +vsram_bus_TB_v +IA=m;kT@ reset_done_trigger; + end + end + + initial begin // Initialize Inputs + clk = 0; addr = 0; nwe = 1; ncs = 1; noe = 1; + end + + initial begin // Process for clk + #OFFSET; + forever + begin + clk = 1'b0; + #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1; + #(PERIOD*DUTY_CYCLE); + end + end + + initial begin: TEST_CASE + #10 -> reset_trigger; + @ (reset_done_trigger); + // Write data to SRAM + for(i=0; i<10; i=i+1) begin + @ (posedge clk); + ncs <= 0; + addr <= i[9:0]; + repeat (TSET) begin + @ (posedge clk); + end + nwe <= 0; + sram_data$inout$reg <= i*2; + repeat (NWS) begin + @ (posedge clk); + end + nwe <= 1; + repeat (THLD) begin + @ (posedge clk); + end + ncs <= 1; + sram_data$inout$reg = {16{1'bz}}; + end + nwe = 1; + + //Read Data + for(i=0; i<10; i=i+1) begin + @ (posedge clk); + ncs <= 0; + addr <= i[9:0]; + repeat (TSET) begin + @ (posedge clk); + end + noe <= 0; + sram_data$inout$reg <= i; + repeat (NWS) begin + @ (posedge clk); + end + noe <= 1; + repeat (THLD) begin + @ (posedge clk); + end + ncs <= 1; + sram_data$inout$reg = {16{1'bz}}; + end + end + + +endmodule + diff --git a/plasma/logic/Makefile b/plasma/logic/Makefile index 80de778..df9e656 100644 --- a/plasma/logic/Makefile +++ b/plasma/logic/Makefile @@ -3,11 +3,8 @@ PINS = $(DESIGN).ucf DEVICE = xc3s500e-fg320-4 BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ -g CRC:enable -g StartUpClk:CCLK - - SIM_CMD = /opt/cad/modeltech/bin/vsim SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do -#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd @@ -68,8 +65,15 @@ build/project_r.twr: build/project_r.ncd $(DESIGN).bit: build/project_r.ncd build/project_r.twr cd build && bitgen project_r.ncd -l -w $(BGFLAGS) @mv -f build/project_r.bit $@ -upload: $(DESIGN).bit - LD_PRELOAD=/usr/lib/libusb-driver.so impact -batch prog.cmd + +build/project_r.v: build/project_r.ncd + cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v + +sim: + cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do + +timesim: build/project_r.v + cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do sim: cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do diff --git a/plasma/logic/simulation/plasma_TIMING_TB.do b/plasma/logic/simulation/plasma_TIMING_TB.do new file mode 100644 index 0000000..44138cd --- /dev/null +++ b/plasma/logic/simulation/plasma_TIMING_TB.do @@ -0,0 +1,9 @@ +vlib work +vlog -incr "../build/project.v" "../plasma_TB.v" "glbl.v" +vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver plasma_TB_v glbl +view wave +do wave1.do +#add wave * +view structure +view signals +run 16us