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Adding post route simulation to FPGA examples

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This commit is contained in:
Carlos Camargo
2010-05-10 14:56:51 -05:00
parent 5938d6531c
commit 717c35e238
23 changed files with 404 additions and 15 deletions
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10
Examples/blink/logic/simulation/blink_TIMING_TB.do Normal file
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vlib work
vlog -incr "../build/project.v" "../blink_TB.v" "glbl.v"
vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl
view wave
#do wave.do
add wave *
add wave /glbl/GSR
view structure
view signals
run 15ms