Adding post route simulation to FPGA examples

2025-04-21 12:27:27 +03:00 · 2010-05-10 14:56:51 -05:00
parent 5938d6531c
commit 717c35e238
23 changed files with 404 additions and 15 deletions
--- a/Examples/sram/logic/simulation/sram_bus_TB.do
+++ b/Examples/sram/logic/simulation/sram_bus_TB.do
@@ -0,0 +1,12 @@
+vlib work
+vlog   -incr +libext+.v                    \
+			"../sram_bus.v"       \
+			"../sram_bus_TB.v"    \
+			"glbl.v"
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
+view wave
+#do wave.do
+add wave *
+view structure
+view signals
+run 5us