Adding post route simulation to FPGA examples

2025-04-21 12:27:27 +03:00 · 2010-05-10 14:56:51 -05:00
parent 5938d6531c
commit 717c35e238
23 changed files with 404 additions and 15 deletions
--- a/Examples/sram/logic/simulation/work/glbl/_primary.vhd
+++ b/Examples/sram/logic/simulation/work/glbl/_primary.vhd
@@ -0,0 +1,8 @@
+library verilog;
+use verilog.vl_types.all;
+entity glbl is
+    generic(
+        ROC_WIDTH       : integer := 100000;
+        TOC_WIDTH       : integer := 0
+    );
+end glbl;