Adding post route simulation to FPGA examples

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

@@ -0,0 +1,14 @@
+library verilog;
+use verilog.vl_types.all;
+entity sram_bus is
+    port(
+        clk             : in     vl_logic;
+        reset           : in     vl_logic;
+        ncs             : in     vl_logic;
+        noe             : in     vl_logic;
+        nwe             : in     vl_logic;
+        led             : out    vl_logic;
+        sram_data       : inout  vl_logic_vector(7 downto 0);
+        addr            : in     vl_logic_vector(12 downto 0)
+    );
+end sram_bus;