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git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-04-21 12:27:27 +03:00
Fixing LOGIC example.
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@@ -15,7 +15,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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// synchronize signals
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reg sncs, snwe;
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reg [10:0] buffer_addr;
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reg [12:0] buffer_addr;
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reg [B:0] buffer_data;
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// bram interfaz signals
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@@ -25,7 +25,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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wire [B:0] rdBus;
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// interfaz fpga signals
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wire [10:0] addr;
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wire [12:0] addr;
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reg [25:0] counter;
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@@ -76,14 +76,14 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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wire [3:0] csN;
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wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
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assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000:
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assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
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4'b0100)
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: (buffer_addr[9]? 4'b0010:
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: (buffer_addr[11]? 4'b0010:
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4'b0001);
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assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3:
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assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
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rdBus2)
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: (buffer_addr[9]? rdBus1:
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: (buffer_addr[11]? rdBus1:
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rdBus0);
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// Peripheral instantiation
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@@ -97,7 +97,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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.ADC_SCLK(ADC_SCLK),
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.ADC_SDIN(ADC_SDIN),
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.ADC_SDOUT(ADC_SDOUT),
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.addr(buffer_addr[8:0]),
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.addr(buffer_addr[10:0]),
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.rdBus(rdBus0),
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.wrBus(wrBus),
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.we(we));
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