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Code

Fixing LOGIC example.

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This commit is contained in:
Juan64Bits 2010-04-04 13:58:41 -05:00
parent 062270bbd4
commit 7545f04d37
3 changed files with 90 additions and 71 deletions
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6
Examples/ADC/logic/ADC.ucf
View File

@ -3,8 +3,8 @@ NET reset LOC = "P71"; #WARNING change to another pin
NET led LOC = "P44"; NET led LOC = "P44";
#ADDRESS BUS #ADDRESS BUS
#NET "addr<12>" LOC = "P90"; NET "addr<12>" LOC = "P90";
#NET "addr<11>" LOC = "P91"; NET "addr<11>" LOC = "P91";
NET "addr<10>" LOC = "P85"; NET "addr<10>" LOC = "P85";
NET "addr<9>" LOC = "P92"; NET "addr<9>" LOC = "P92";
NET "addr<8>" LOC = "P94"; NET "addr<8>" LOC = "P94";
@ -38,4 +38,4 @@ NET "ADC_SCLK" LOC = "P18" ;
NET "ADC_SDIN" LOC = "P22"; NET "ADC_SDIN" LOC = "P22";
NET "ADC_SDOUT" LOC = "P23"; NET "ADC_SDOUT" LOC = "P23";
NET "ADC_CS" LOC = "P24"; NET "ADC_CS" LOC = "P24";
NET "ADC_CSTART" LOC = "P26"; NET "ADC_CSTART" LOC = "P26";

14
Examples/ADC/logic/ADC.v
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@ -15,7 +15,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
// synchronize signals // synchronize signals
reg sncs, snwe; reg sncs, snwe;
reg [10:0] buffer_addr; reg [12:0] buffer_addr;
reg [B:0] buffer_data; reg [B:0] buffer_data;
// bram interfaz signals // bram interfaz signals
@ -25,7 +25,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
wire [B:0] rdBus; wire [B:0] rdBus;
// interfaz fpga signals // interfaz fpga signals
wire [10:0] addr; wire [12:0] addr;
reg [25:0] counter; reg [25:0] counter;
@ -76,14 +76,14 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
wire [3:0] csN; wire [3:0] csN;
wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3; wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000: assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
4'b0100) 4'b0100)
: (buffer_addr[9]? 4'b0010: : (buffer_addr[11]? 4'b0010:
4'b0001); 4'b0001);
assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3: assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
rdBus2) rdBus2)
: (buffer_addr[9]? rdBus1: : (buffer_addr[11]? rdBus1:
rdBus0); rdBus0);
// Peripheral instantiation // Peripheral instantiation
@ -97,7 +97,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
.ADC_SCLK(ADC_SCLK), .ADC_SCLK(ADC_SCLK),
.ADC_SDIN(ADC_SDIN), .ADC_SDIN(ADC_SDIN),
.ADC_SDOUT(ADC_SDOUT), .ADC_SDOUT(ADC_SDOUT),
.addr(buffer_addr[8:0]), .addr(buffer_addr[10:0]),
.rdBus(rdBus0), .rdBus(rdBus0),
.wrBus(wrBus), .wrBus(wrBus),
.we(we)); .we(we));

141
Examples/ADC/logic/ADC_peripheral.v
View File

@ -4,39 +4,53 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
addr, rdBus, wrBus, we); addr, rdBus, wrBus, we);
input clk, reset, ADC_EOC, cs, we; input clk, reset, ADC_EOC, cs, we;
input [8:0] addr; input [10:0] addr;
input [7:0] wrBus; input [7:0] wrBus;
output ADC_CS, ADC_CSTART, ADC_SCLK; output ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] rdBus; output [7:0] rdBus;
inout ADC_SDIN, ADC_SDOUT; inout ADC_SDIN, ADC_SDOUT;
//RAMB registers
reg [7:0] rdBus;
wire [7:0] rdBus1;
wire [7:0] rdBus2; wire [7:0] rdBus2;
reg [7:0] wrBus2; reg [7:0] wrBus2;
reg [8:0] addr2; reg [10:0] addr2;
wire we1; reg we1=0;
reg we2=0, nSample=0; reg we2=0;
reg [7:0] auto_count=0; wire we;
//Control registers
reg nSample=0;
reg [10:0] auto_count=0;
reg [4:0] w_st2=0; reg [4:0] w_st2=0;
//SPI registers
reg [3:0] SPI_in_data=0; reg [3:0] SPI_in_data=0;
reg [9:0] SPI_out_data; reg [9:0] SPI_out_data;
reg SPI_rd = 0; reg SPI_rd = 0;
reg SPI_wr = 0; reg SPI_wr = 0;
reg [7:0] buffer_rd1;
reg [3:0] ADC_cmd;
assign we1 = we & cs;
// Confiuration registers
reg CMD_DONE;
reg CMD_TYP;
reg [3:0] CMD_ADC;
reg [7:0] CLKDIV = 0;
reg [10:0] SIZEB; //[10:8] -> size_hi | [7:0] -> size_low
//TEMPS
reg [10:0] SIZEB2;
reg CMD_DONE2;
assign ADC_CSTART = 1'b1; assign ADC_CSTART = 1'b1;
// Dual-port RAM instatiation // Dual-port RAM instatiation
RAMB16_S9_S9 ba0( RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output .DOA(rdBus1), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output .DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output .DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output .DOPB(), // Port B 1-bit Parity Output
.ADDRA(addr[8:0]), // Port A 11-bit Address Input .ADDRA(addr[10:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input .ADDRB(addr2[10:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock .CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock .CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input .DIA(wrBus), // Port A 8-bit Data Input
@ -58,12 +72,11 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
reg [3:0] in_buffer=0; reg [3:0] in_buffer=0;
reg [9:0] out_buffer; reg [9:0] out_buffer;
reg [7:0] clkcount = 0; reg [7:0] clkcount = 0;
reg [7:0] clkdiv = 255;
reg [4:0] count = 0; reg [4:0] count = 0;
assign ADC_CS = ~busy; assign ADC_CS = ~busy;
always@(SPI_rd or out_buffer or busy or clkdiv) always@(SPI_rd or out_buffer or busy or CLKDIV)
begin begin
SPI_out_data = 10'bx; SPI_out_data = 10'bx;
if(SPI_rd) if(SPI_rd)
@ -80,7 +93,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
else else
begin begin
clkcount = clkcount + 1; clkcount = clkcount + 1;
if(clkcount >= clkdiv) if(clkcount >= CLKDIV)
begin begin
clkcount = 0; clkcount = 0;
// Send the ADC CMD on first 4 rising edge of SCLK // Send the ADC CMD on first 4 rising edge of SCLK
@ -113,46 +126,63 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
assign ADC_SCLK = ADC_SCLK_buffer; assign ADC_SCLK = ADC_SCLK_buffer;
assign ADC_SDIN = ADC_SDIN_buffer; assign ADC_SDIN = ADC_SDIN_buffer;
// State Machine for control ADC comunication // Write control
always @(negedge clk)
if(reset)
{CMD_TYP,CMD_ADC,SIZEB,we1} <= 0;
else if(we & cs) begin
case (addr)
0: begin CMD_TYP <= wrBus[4];
CMD_ADC[3:0] <= wrBus[3:0]; end
1: begin CLKDIV <= wrBus; end
2: begin SIZEB[7:0] <= wrBus; end
3: begin SIZEB[10:8] <= wrBus[2:0]; end
default: begin we1 <= 1; end
endcase
end
else if(nSample)
begin SIZEB <= SIZEB - 1; end
else
begin we1 <= 0; end
// Read control
always @(posedge clk)
if(reset)
{rdBus} <= 0;
else begin
case (addr)
0: begin rdBus <= {CMD_DONE,CMD_TYP,CMD_ADC};end
1: begin rdBus <= CLKDIV; end
2: begin rdBus <= SIZEB[7:0]; end
3: begin rdBus <= SIZEB[10:8]; end
default: begin rdBus <= rdBus1; end
endcase
end
// Comunication control
always @(posedge clk) always @(posedge clk)
if(reset) if(reset)
{we2, SPI_wr, SPI_rd, w_st2, auto_count, SPI_in_data} <= 0; {we2, SPI_wr, SPI_rd, w_st2, auto_count, SPI_in_data, nSample} <= 0;
else begin else begin
case (w_st2) case (w_st2)
0: begin addr2 <= 0; w_st2 <= 1; end 0: begin w_st2 <= 2; SIZEB2<=SIZEB; end
1: begin
ADC_cmd <= rdBus2[3:0];
if (rdBus2[7:4] == 5)
// Send command without read samples
begin addr2<= 2; w_st2 <= 2; nSample <= 1; end
else if (rdBus2[7:4] == 6)
// Read: Stop when buffer full
begin addr2<= 2; w_st2 <= 2; nSample <= 0; end
else if (rdBus2[7:4] == 9)
// Set clkdiv on SPI controller
begin addr2<= 1; w_st2 <= 10; end
else
begin w_st2 <= 0; end
end
2: begin 2: begin
if (rdBus2[7:0] == 0) if (SIZEB == 0)
begin auto_count<=0; w_st2 <= 0; end begin w_st2 <= 0; CMD_DONE<= 1; auto_count <= 0; end
else begin else begin
CMD_DONE<= 0;
//Send data to ADC //Send data to ADC
buffer_rd1<=rdBus2; auto_count <= auto_count+1;
auto_count<=auto_count+1; SPI_in_data <= CMD_ADC[3:0];
SPI_in_data <= ADC_cmd[3:0]; SPI_wr <= 1; w_st2 <= 3;
SPI_wr <= 1; w_st2 <= 3;
end end
end end
3: begin 3: begin
SPI_wr <= 0; SPI_wr <= 0;
//Wait for complete convertion //Wait for complete convertion
if(!ADC_EOC || ADC_CS) begin if(!ADC_EOC || ADC_CS) begin
buffer_rd1<=buffer_rd1-1;
SPI_rd <=1; SPI_rd <=1;
if(nSample) if(CMD_TYP)
w_st2<= 8; w_st2<= 2;
else else
w_st2<= 4; w_st2<= 4;
end end
@ -160,29 +190,18 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
4: begin 4: begin
//Write data on BRAM (LOW) //Write data on BRAM (LOW)
wrBus2 <= SPI_out_data[7:0]; wrBus2 <= SPI_out_data[7:0];
addr2 <= 2+2*auto_count; addr2 <= 4+2*(SIZEB2-SIZEB);
we2 <= 1; w_st2 <= 5; we2 <= 1; w_st2 <= 5;
end end
5: begin we2 <= 0; w_st2 <= 6; end 5: begin we2 <= 0; w_st2 <= 6; end
6: begin 6: begin
//Write data on BRAM (HI) //Write data on BRAM (HI)
wrBus2 <= SPI_out_data[9:8]; wrBus2 <= SPI_out_data[9:8];
addr2 <= 3+2*auto_count; addr2 <= 5+2*(SIZEB2-SIZEB);
we2 <= 1; w_st2 <= 7; we2 <= 1; w_st2 <= 7; nSample <= 1;
end end
7: begin we2 <= 0; w_st2 <= 8; end 7: begin nSample <= 0; we2 <= 0; SPI_rd <=0; w_st2 <= 2; end
8: begin
SPI_rd <=0;
//Update Buffer Size value
wrBus2 <= buffer_rd1;
addr2 <= 2;
we2 <= 1; w_st2 <= 9;
end
9: begin we2 <= 0; w_st2 <= 0; end
//Sent clock divider for speed on SPI comunication
10: begin clkdiv = rdBus2; w_st2 <= 0; end
endcase endcase
end end
endmodule endmodule