From 7a27846dca89ea005814caf140dfa46973e74822 Mon Sep 17 00:00:00 2001 From: afc Date: Thu, 18 Mar 2010 08:18:01 -0500 Subject: [PATCH] SRAM fixed to 4 BRAM (8KB) --- Examples/sram/logic/sram_bus.v | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/Examples/sram/logic/sram_bus.v b/Examples/sram/logic/sram_bus.v index 233e050..b5f4e1f 100644 --- a/Examples/sram/logic/sram_bus.v +++ b/Examples/sram/logic/sram_bus.v @@ -6,9 +6,6 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led); inout [B:0] sram_data; output led; -// Internal conection - wire led; - // synchronize signals reg sncs, snwe; reg [12:0] buffer_addr; @@ -59,13 +56,22 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led); endcase end -RAMB16_S18 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), - .WE(we), .DIP(2'b00), .DI(wdBus), .DO(rdBus) ); +RAMB16_S2 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), + .WE(we), .DI(wdBus[1:0]), .DO(rdBus[1:0]) ); - reg [32:0] counter; +RAMB16_S2 ba1( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), + .WE(we), .DI(wdBus[3:2]), .DO(rdBus[3:2]) ); + +RAMB16_S2 ba2( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), + .WE(we), .DI(wdBus[5:4]), .DO(rdBus[5:4]) ); + +RAMB16_S2 ba3( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr), + .WE(we), .DI(wdBus[7:6]), .DO(rdBus[7:6]) ); + + reg [24:0] counter; always @(posedge clk) begin if (reset) - counter <= {32{1'b0}}; + counter <= {25{1'b0}}; else counter <= counter + 1; end