diff --git a/Examples/ADC/Scope-QT-src/ADC b/Examples/ADC/Scope-QT-src/ADC index 96016a3..837224e 100755 Binary files a/Examples/ADC/Scope-QT-src/ADC and b/Examples/ADC/Scope-QT-src/ADC differ diff --git a/Examples/ADC/Scope-QT-src/ADCw.cpp b/Examples/ADC/Scope-QT-src/ADCw.cpp index a295184..a9e9453 100644 --- a/Examples/ADC/Scope-QT-src/ADCw.cpp +++ b/Examples/ADC/Scope-QT-src/ADCw.cpp @@ -2,9 +2,10 @@ ADCw::ADCw() { - BUFFER_OFFSET = 8; + BUFFER_OFFSET = 9; ADC_SPI_CLKDIV=ADC_SPI_CLKDIV_MAX; //Set clock to minimum speed - BUFFER_LEN=10; + BUFFER_LEN=16; + MUX_CHANNELS =0; ADCBuffer = jz_adc_init(); @@ -25,7 +26,6 @@ void ADCw::testADC() printf("\nINIT TEST1: Autoselft {(Vref+) - (Vref-)}/2 -> Return 0x0200 \n"); adcConfig(ADC_CMD_SET_AUTOSELFT_1); adcConfig(ADC_CMD_READ_AUTOSELFT_1); - while(adcCheckBufferFull())usleep (10); for(int i=BUFFER_OFFSET; i< BUFFER_LEN/2+BUFFER_OFFSET; i++) printf("[%08X]", ADCBuffer[i]); fflush (stdout); @@ -34,7 +34,6 @@ void ADCw::testADC() printf("\n\nINIT TEST2: Autoselft (Vref-) -> Return 0x0000 \n"); adcConfig(ADC_CMD_SET_AUTOSELFT_2); adcConfig(ADC_CMD_READ_AUTOSELFT_2); - while(adcCheckBufferFull())usleep (10); for(int i=BUFFER_OFFSET; i< BUFFER_LEN/2+BUFFER_OFFSET; i++) printf("[%08X]", ADCBuffer[i]); fflush (stdout); @@ -60,17 +59,18 @@ JZ_REG* ADCw::takeSamplesADC(int CHANNEL) { adcConfig(ADC_CMD_SET_CHANNEL0+CHANNEL); adcConfig(ADC_CMD_READ_CHANNEL0+CHANNEL); - while(adcCheckBufferFull())usleep (10); return (JZ_REG*)(ADCBuffer+BUFFER_OFFSET); } void ADCw::adcConfig(uchar CMD) { - ADCBuffer[0] = ((BUFFER_LEN+(BUFFER_OFFSET-1)*2) << 16) + (ADC_SPI_CLKDIV<<8) + CMD; - usleep (100); + ADCBuffer[0] = (((MUX_CHANNELS<<6) + CMD)<<24) + \ + ((BUFFER_LEN+(BUFFER_OFFSET-1)*2) << 8) + \ + (ADC_SPI_CLKDIV); + while(adcCheckBufferFull()) usleep (10); } int ADCw::adcCheckBufferFull() { - return ADCBuffer[0]&0x20; + return ADCBuffer[0]&0x20000000; } diff --git a/Examples/ADC/Scope-QT-src/ADCw.h b/Examples/ADC/Scope-QT-src/ADCw.h index 83eedb7..4495aba 100644 --- a/Examples/ADC/Scope-QT-src/ADCw.h +++ b/Examples/ADC/Scope-QT-src/ADCw.h @@ -16,7 +16,7 @@ public: JZ_REG * takeSamplesADC(int CHANNEL); void setClockDiv(uchar value){ ADC_SPI_CLKDIV = value;} void setBufferLen(int value){ BUFFER_LEN = value;} - + void setMuxChannels(uchar value){ MUX_CHANNELS = value;} private: void adcConfig(uchar CMD); int adcCheckBufferFull(); @@ -25,6 +25,7 @@ private: uchar ADC_SPI_CLKDIV; int BUFFER_LEN; int BUFFER_OFFSET; + uchar MUX_CHANNELS; }; #endif // ADCW_H diff --git a/Examples/ADC/Scope-QT-src/Makefile b/Examples/ADC/Scope-QT-src/Makefile index b624c46..88adf3d 100644 --- a/Examples/ADC/Scope-QT-src/Makefile +++ b/Examples/ADC/Scope-QT-src/Makefile @@ -1,6 +1,6 @@ ############################################################################# # Makefile for building: ADC -# Generated by qmake (2.01a) (Qt 4.6.2) on: Fri Apr 9 10:33:37 2010 +# Generated by qmake (2.01a) (Qt 4.6.2) on: Mon Apr 12 21:21:04 2010 # Project: ADC1.pro # Template: app # Command: /home/juan64bits/ebd/ECB/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/bin/qmake -spec ../../../../openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/mkspecs/qws/linux-openwrt-g++ -unix -o Makefile ADC1.pro diff --git a/Examples/ADC/Scope-QT-src/jz_adc_peripheral.h b/Examples/ADC/Scope-QT-src/jz_adc_peripheral.h index 9617df2..e672bd1 100644 --- a/Examples/ADC/Scope-QT-src/jz_adc_peripheral.h +++ b/Examples/ADC/Scope-QT-src/jz_adc_peripheral.h @@ -25,6 +25,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #define ADC_CMD_NONE 0x00 /* Nothing to do */ #define ADC_CMD_SET_SPI_CLKDIV 0x00 /* Set clock divider for ADC sclk */ +#define ADC_CMD_SET_BUFFER_SIZE 0x00 /* Set clock divider for ADC sclk */ #define ADC_CMD_SET_CHANNEL0 0x30 /* Set channel 0 */ #define ADC_CMD_READ_CHANNEL0 0x20 /* Read channel 0 */ @@ -68,7 +69,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #define ADC_SPI_CLKDIV_MIN 0x08 /* 50/(2*9) -> 2.78MHz (MAX=2.8MHz) */ #define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*256) -> 97.65KHz */ -#define ADC_MAX_BUFFER 0x3F0/* 1008 reads/commands */ +#define ADC_MAX_BUFFER 0x3FE/* 1022 reads/commands */ #define CS2_PORT JZ_GPIO_PORT_B #define CS2_PIN 26 diff --git a/Examples/ADC/Scope-QT-src/mainwindow.cpp b/Examples/ADC/Scope-QT-src/mainwindow.cpp index 0c6da83..f6fbbe2 100755 --- a/Examples/ADC/Scope-QT-src/mainwindow.cpp +++ b/Examples/ADC/Scope-QT-src/mainwindow.cpp @@ -17,12 +17,12 @@ MainWindow::MainWindow(QWidget *parent) timer1->start(50); connect(timer1, SIGNAL(timeout()), this, SLOT(updateGraph())); - CHANNEL = 1; ADC1 = new ADCw; ADC1->testADC(); - ADC1->setBufferLen(120); - ADC1->setClockDiv(ADC_SPI_CLKDIV_MAX); //Maximun speed - printf("\nTaking 300 samples each 50ms from Channel 0,1 at Fs=99KHz \n"); + ADC1->setBufferLen(240); + ADC1->setClockDiv(ADC_SPI_CLKDIV_MIN); //Max. speed + ADC1->setMuxChannels(1); + printf("\nTaking 120 samples by channel at Fs=99KHz (trigger=50ms)\n"); } MainWindow::~MainWindow() @@ -36,26 +36,12 @@ void MainWindow::updateGraph() int tempD; - //CHANNEL 0 dataADC=ADC1->takeSamplesADC(0); - for(int i=0; i< 120/2; i++) - { - //printf("[%08X]",dataADC[i]); - tempD = dataADC[i]&0xFFFF; + for(int i=0; i< 240/2; i++) + { + tempD = dataADC[i]&0x0FFF; ui->Graph->addPoint1(tempD+0x3ff); - tempD = dataADC[i]>>16; - ui->Graph->addPoint1(tempD+0x3ff); - } - CHANNEL = 1; - - //CHANNEL 1 - dataADC=ADC1->takeSamplesADC(1); - for(int i=0; i< 120/2; i++) - { - //printf("[%08X]",dataADC[i]); - tempD = dataADC[i]&0xFFFF; - ui->Graph->addPoint2(tempD); - tempD = dataADC[i]>>16; + tempD = (dataADC[i]>>16)&0x0FFF; ui->Graph->addPoint2(tempD); } diff --git a/Examples/ADC/logic/ADC.bit b/Examples/ADC/logic/ADC.bit index b984bf9..646695d 100644 Binary files a/Examples/ADC/logic/ADC.bit and b/Examples/ADC/logic/ADC.bit differ diff --git a/Examples/ADC/logic/ADC_peripheral.v b/Examples/ADC/logic/ADC_peripheral.v index 185ae3a..a19d5ca 100644 --- a/Examples/ADC/logic/ADC_peripheral.v +++ b/Examples/ADC/logic/ADC_peripheral.v @@ -27,17 +27,22 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, reg fullB=0; reg rstStart=0; reg [2:0] w_st0=0; - reg w_st1=0; + reg [2:0] w_st1=0; reg [2:0] w_st2=0; // Confiuration registers - reg CMD_START=0; - reg CMD_TYP=0; - reg [3:0] CMD_ADC=0; - reg [7:0] CLKDIV = 0; - reg [9:0] SIZEB=0; //[10:8] -> size_hi | [7:0] -> size_low + reg [1:0] CMD_SW=0; // Channel offset selection + reg CMD_START=0; // START sampling data + reg CMD_TYP=0; // Command type + reg [3:0] CMD_ADC=0; // ADC command + reg [7:0] CLKDIV = 0; // Clock divisor for SPI + reg [9:0] SIZEB=0; // Buffer size (sampling data len.) //TEMPS - reg [9:0] SIZEB2=0; + reg [9:0] SIZEB1=0; // Temporal for buffer size + reg [9:0] SIZEB2=0; // Temporal for buffer size + reg [2:0] CMD_OFFSET=0; // Channel offset counter MOD8 + wire[2:0] CMD_OFFSETt; // Channel offset to use + wire[3:0] CMD_ADCt; // Temporal for channel offset assign ADC_CSTART = 1'b1; @@ -128,7 +133,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, // SPI Transmitter always@(posedge clk) begin - if(load_in) in_buffer <= CMD_ADC[3:0]; + if(load_in) in_buffer <= CMD_ADCt[3:0]; if(!fallingSCLK & pulse) begin ADC_SDIN_buffer <= in_buffer[3]; in_buffer <= in_buffer << 1; @@ -142,22 +147,26 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, // REGISTER BANK: Write control always @(negedge clk) + begin if(reset) {CMD_START, CMD_TYP,CMD_ADC,SIZEB,we1} <= 0; else if(we & cs) begin case (addr) - 0: begin CMD_START <= wrBus[5]; + 0: begin CLKDIV[7:0] <= wrBus; end + 1: begin SIZEB[7:0] <= wrBus; end + 2: begin SIZEB[9:8] <= wrBus[1:0]; end + 3: begin CMD_SW[1:0] <= wrBus[7:6]; + CMD_START <= wrBus[5]; CMD_TYP <= wrBus[4]; CMD_ADC[3:0] <= wrBus[3:0]; end - 1: begin CLKDIV <= wrBus; end - 2: begin SIZEB[7:0] <= wrBus; end - 3: begin SIZEB[9:8] <= wrBus[1:0]; end default: begin we1 <= 1; end endcase - end else if(fullB || rstStart) begin - CMD_START <= 0; end + end else begin - we1 <= 0; end + we1 <= 0; end + + if(fullB | rstStart) CMD_START <= 0; + end // REGISTER BANK: Read control always @(posedge clk) @@ -165,10 +174,10 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, {rdBus} <= 0; else begin case (addr) - 0: begin rdBus <= {CMD_START,CMD_TYP,CMD_ADC};end - 1: begin rdBus <= CLKDIV; end - 2: begin rdBus <= SIZEB[7:0]; end - 3: begin rdBus <= SIZEB[9:8]; end + 0: begin rdBus <= CLKDIV; end + 1: begin rdBus <= SIZEB[7:0]; end + 2: begin rdBus <= SIZEB[9:8]; end + 3: begin rdBus <= {CMD_SW,CMD_START,CMD_TYP,CMD_ADC};end default: begin rdBus <= rdBus1; end endcase end @@ -176,22 +185,22 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, // CONTROL always @(posedge clk) if(reset) begin - {w_st0, SPI_wr} <= 0; + {w_st0, SPI_wr, loadB, initB} <= 0; ADC_CS <=1; end else begin case (w_st0) 0: begin - rstStart <= 0; loadB <= 0; initB<=0; + rstStart <= 0; if(CMD_START) begin ADC_CS <=0; SPI_wr <= 1; w_st0 <=1; end end - 1: begin - SPI_wr <= 0; - if(!busy && ADC_EOC) begin + 1: begin SPI_wr <= 0; w_st0 <=2; end + 2: begin + if(!busy & ADC_EOC) begin ADC_CS <=1; if(CMD_TYP) begin rstStart <= 1; @@ -199,31 +208,33 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, end else begin initB<=1; - w_st0<= 2; + w_st0<= 3; end end - end - 2: begin loadB <= 1; w_st0<= 0; end + end + 3: begin loadB <= 1; w_st0<= 4; end + 4: begin loadB <= 0; initB<=0; w_st0<= 0; end endcase end // Reception Buffer always @(posedge clk) if(reset) - {we2, w_st2, fullB, SIZEB2} <= 0; + {we2, w_st2, fullB, SIZEB1, SIZEB2} <= 0; else begin case (w_st2) 0: begin fullB <= 0; if(initB) begin w_st2 <= 1; + SIZEB1<=SIZEB; SIZEB2<=SIZEB; end - end + end 1: begin if(loadB) begin // If buffer full set fullB flag by a clock cicle - if(SIZEB2) begin + if(SIZEB2>0) begin w_st2 <= 2; end else begin fullB <= 1; @@ -233,15 +244,15 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, end 2: begin //Write data on BRAM (LOW) - wrBus2 <= out_buffer[7:0]; - addr2 <= 4+2*(SIZEB-SIZEB2); + wrBus2[7:0] <= out_buffer[7:0]; + addr2 <= 4+2*(SIZEB1-SIZEB2); we2 <= 1; w_st2 <= 3; end 3: begin we2 <= 0; w_st2 <= 4; end 4: begin //Write data on BRAM (HI) - wrBus2 <= out_buffer[9:8]; - addr2 <= 5+2*(SIZEB-SIZEB2); + wrBus2[7:0] <= {CMD_OFFSETt,2'b00,out_buffer[9:8]}; + addr2 <= 5+2*(SIZEB1-SIZEB2); we2 <= 1; w_st2 <= 5; end 5: begin @@ -249,5 +260,21 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART, end endcase end - + + // ADC channel offset, counter MOD8 + always @(posedge clk) + if(fullB | reset) + CMD_OFFSET <= 0; + else if(loadB) begin + CMD_OFFSET <= CMD_OFFSET + 1; + end + + // MUX to select the channel offset + assign CMD_OFFSETt = CMD_SW[1]? (CMD_SW[0]? CMD_OFFSET[2:0] : + CMD_OFFSET[1:0] ) + : (CMD_SW[0]? CMD_OFFSET[0] : + 3'b0 ); + + // Add ADC command and offset + assign CMD_ADCt = CMD_ADC + CMD_OFFSETt; endmodule diff --git a/Examples/ADC/logic/ADC_peripheral_tb.v b/Examples/ADC/logic/ADC_peripheral_tb.v new file mode 100644 index 0000000..1b9f322 --- /dev/null +++ b/Examples/ADC/logic/ADC_peripheral_tb.v @@ -0,0 +1,263 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:22:07 04/12/2010 +// Design Name: ADC_peripheral +// Module Name: /home/juan64bits/ebd/ECB/nn-usb-fpga/Examples/ADC/logicISE/ADC_peripheral_tb.v +// Project Name: logicISE +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: ADC_peripheral +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module ADC_peripheral_tb; + + // Inputs + reg clk; + reg reset; + reg cs; + reg ADC_EOC; + reg [10:0] addr; + reg [7:0] wrBus; + reg we; + + // Outputs + wire ADC_CS; + wire ADC_CSTART; + wire ADC_SCLK; + wire [7:0] rdBus; + + // Bidirs + wire ADC_SDIN; + wire ADC_SDOUT; + + // Instantiate the Unit Under Test (UUT) + ADC_peripheral uut ( + .clk(clk), + .reset(reset), + .cs(cs), + .ADC_EOC(ADC_EOC), + .ADC_CS(ADC_CS), + .ADC_CSTART(ADC_CSTART), + .ADC_SCLK(ADC_SCLK), + .ADC_SDIN(ADC_SDIN), + .ADC_SDOUT(ADC_SDOUT), + .addr(addr), + .rdBus(rdBus), + .wrBus(wrBus), + .we(we) + ); + + initial begin + // Initialize Inputs + clk = 0; + reset = 0; + cs = 0; + ADC_EOC = 1; + addr = 0; + wrBus = 0; + we = 0; + + // Wait 100 ns for global reset to finish + #100; + + addr = 0; + wrBus = 1; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 1; + wrBus = 8; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 2; + wrBus = 0; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 3; + wrBus = 0; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 3; + wrBus = 8'h39; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 1; + #20; + + while(rdBus[5]) + begin + #20; + end + #100; + addr = 3; + wrBus = 8'h39; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 1; + #20; + + while(rdBus[5]) + begin + #20; + end + #100; + addr = 0; + wrBus = 2; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 1; + wrBus = 10; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 2; + wrBus = 0; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 3; + wrBus = 8'h2B; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 1; + #20; + + while(rdBus[5]) + begin + #20; + end + #100; + + addr = 1; + wrBus = 15; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 3; + wrBus = 8'h2C; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 1; + #20; + + while(rdBus[5]) + begin + #20; + end + #100; + + addr = 1; + wrBus = 20; + we = 1; + cs = 1; + #20; + addr = 0; + wrBus = 0; + we = 0; + cs = 0; + #20; + + addr = 3; + wrBus = 8'h2D; + we = 1; + cs = 1; + #20; + addr = 3; + wrBus = 0; + we = 0; + cs = 1; + #20; + + while(rdBus[5]) + begin + #20; + end + #100; + end + +// Match Xport 2.0 50 MHz clock on FPGA (20ns period) +always begin clk = ~clk; #10; end + +endmodule + diff --git a/docs/wiki/.~lock.ADC.odg# b/docs/wiki/.~lock.ADC.odg# new file mode 100644 index 0000000..0215ba5 --- /dev/null +++ b/docs/wiki/.~lock.ADC.odg# @@ -0,0 +1 @@ +Juan64Bits ,juan64bits,Maximus,12.04.2010 16:34,file:///home/juan64bits/.openoffice.org/3; \ No newline at end of file diff --git a/docs/wiki/ADC.odg b/docs/wiki/ADC.odg index 43f4f28..1bf0da8 100644 Binary files a/docs/wiki/ADC.odg and b/docs/wiki/ADC.odg differ