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Fixing multi-channel mode.

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Juan64Bits
2010-04-12 21:26:26 -05:00
parent beca2e0bd3
commit 7a462423ed
11 changed files with 347 additions and 68 deletions
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Examples/ADC/logic/ADC.bit
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97
Examples/ADC/logic/ADC_peripheral.v
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@@ -27,17 +27,22 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
reg fullB=0;
reg rstStart=0;
reg [2:0] w_st0=0;
reg w_st1=0;
reg [2:0] w_st1=0;
reg [2:0] w_st2=0;
// Confiuration registers
reg CMD_START=0;
reg CMD_TYP=0;
reg [3:0] CMD_ADC=0;
reg [7:0] CLKDIV = 0;
reg [9:0] SIZEB=0; //[10:8] -> size_hi | [7:0] -> size_low
reg [1:0] CMD_SW=0; // Channel offset selection
reg CMD_START=0; // START sampling data
reg CMD_TYP=0; // Command type
reg [3:0] CMD_ADC=0; // ADC command
reg [7:0] CLKDIV = 0; // Clock divisor for SPI
reg [9:0] SIZEB=0; // Buffer size (sampling data len.)
//TEMPS
reg [9:0] SIZEB2=0;
reg [9:0] SIZEB1=0; // Temporal for buffer size
reg [9:0] SIZEB2=0; // Temporal for buffer size
reg [2:0] CMD_OFFSET=0; // Channel offset counter MOD8
wire[2:0] CMD_OFFSETt; // Channel offset to use
wire[3:0] CMD_ADCt; // Temporal for channel offset
assign ADC_CSTART = 1'b1;
@@ -128,7 +133,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
// SPI Transmitter
always@(posedge clk)
begin
if(load_in) in_buffer <= CMD_ADC[3:0];
if(load_in) in_buffer <= CMD_ADCt[3:0];
if(!fallingSCLK & pulse) begin
ADC_SDIN_buffer <= in_buffer[3];
in_buffer <= in_buffer << 1;
@@ -142,22 +147,26 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
// REGISTER BANK: Write control
always @(negedge clk)
begin
if(reset)
{CMD_START, CMD_TYP,CMD_ADC,SIZEB,we1} <= 0;
else if(we & cs) begin
case (addr)
0: begin CMD_START <= wrBus[5];
0: begin CLKDIV[7:0] <= wrBus; end
1: begin SIZEB[7:0] <= wrBus; end
2: begin SIZEB[9:8] <= wrBus[1:0]; end
3: begin CMD_SW[1:0] <= wrBus[7:6];
CMD_START <= wrBus[5];
CMD_TYP <= wrBus[4];
CMD_ADC[3:0] <= wrBus[3:0]; end
1: begin CLKDIV <= wrBus; end
2: begin SIZEB[7:0] <= wrBus; end
3: begin SIZEB[9:8] <= wrBus[1:0]; end
default: begin we1 <= 1; end
endcase
end else if(fullB || rstStart) begin
CMD_START <= 0; end
end
else begin
we1 <= 0; end
we1 <= 0; end
if(fullB | rstStart) CMD_START <= 0;
end
// REGISTER BANK: Read control
always @(posedge clk)
@@ -165,10 +174,10 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
{rdBus} <= 0;
else begin
case (addr)
0: begin rdBus <= {CMD_START,CMD_TYP,CMD_ADC};end
1: begin rdBus <= CLKDIV; end
2: begin rdBus <= SIZEB[7:0]; end
3: begin rdBus <= SIZEB[9:8]; end
0: begin rdBus <= CLKDIV; end
1: begin rdBus <= SIZEB[7:0]; end
2: begin rdBus <= SIZEB[9:8]; end
3: begin rdBus <= {CMD_SW,CMD_START,CMD_TYP,CMD_ADC};end
default: begin rdBus <= rdBus1; end
endcase
end
@@ -176,22 +185,22 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
// CONTROL
always @(posedge clk)
if(reset) begin
{w_st0, SPI_wr} <= 0;
{w_st0, SPI_wr, loadB, initB} <= 0;
ADC_CS <=1;
end
else begin
case (w_st0)
0: begin
rstStart <= 0; loadB <= 0; initB<=0;
rstStart <= 0;
if(CMD_START) begin
ADC_CS <=0;
SPI_wr <= 1;
w_st0 <=1;
end
end
1: begin
SPI_wr <= 0;
if(!busy && ADC_EOC) begin
1: begin SPI_wr <= 0; w_st0 <=2; end
2: begin
if(!busy & ADC_EOC) begin
ADC_CS <=1;
if(CMD_TYP) begin
rstStart <= 1;
@@ -199,31 +208,33 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
end
else begin
initB<=1;
w_st0<= 2;
w_st0<= 3;
end
end
end
2: begin loadB <= 1; w_st0<= 0; end
end
3: begin loadB <= 1; w_st0<= 4; end
4: begin loadB <= 0; initB<=0; w_st0<= 0; end
endcase
end
// Reception Buffer
always @(posedge clk)
if(reset)
{we2, w_st2, fullB, SIZEB2} <= 0;
{we2, w_st2, fullB, SIZEB1, SIZEB2} <= 0;
else begin
case (w_st2)
0: begin
fullB <= 0;
if(initB) begin
w_st2 <= 1;
SIZEB1<=SIZEB;
SIZEB2<=SIZEB;
end
end
end
1: begin
if(loadB) begin
// If buffer full set fullB flag by a clock cicle
if(SIZEB2) begin
if(SIZEB2>0) begin
w_st2 <= 2; end
else begin
fullB <= 1;
@@ -233,15 +244,15 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
end
2: begin
//Write data on BRAM (LOW)
wrBus2 <= out_buffer[7:0];
addr2 <= 4+2*(SIZEB-SIZEB2);
wrBus2[7:0] <= out_buffer[7:0];
addr2 <= 4+2*(SIZEB1-SIZEB2);
we2 <= 1; w_st2 <= 3;
end
3: begin we2 <= 0; w_st2 <= 4; end
4: begin
//Write data on BRAM (HI)
wrBus2 <= out_buffer[9:8];
addr2 <= 5+2*(SIZEB-SIZEB2);
wrBus2[7:0] <= {CMD_OFFSETt,2'b00,out_buffer[9:8]};
addr2 <= 5+2*(SIZEB1-SIZEB2);
we2 <= 1; w_st2 <= 5;
end
5: begin
@@ -249,5 +260,21 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
end
endcase
end
// ADC channel offset, counter MOD8
always @(posedge clk)
if(fullB | reset)
CMD_OFFSET <= 0;
else if(loadB) begin
CMD_OFFSET <= CMD_OFFSET + 1;
end
// MUX to select the channel offset
assign CMD_OFFSETt = CMD_SW[1]? (CMD_SW[0]? CMD_OFFSET[2:0] :
CMD_OFFSET[1:0] )
: (CMD_SW[0]? CMD_OFFSET[0] :
3'b0 );
// Add ADC command and offset
assign CMD_ADCt = CMD_ADC + CMD_OFFSETt;
endmodule

263
Examples/ADC/logic/ADC_peripheral_tb.v Normal file
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@@ -0,0 +1,263 @@
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:22:07 04/12/2010
// Design Name: ADC_peripheral
// Module Name: /home/juan64bits/ebd/ECB/nn-usb-fpga/Examples/ADC/logicISE/ADC_peripheral_tb.v
// Project Name: logicISE
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ADC_peripheral
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ADC_peripheral_tb;
// Inputs
reg clk;
reg reset;
reg cs;
reg ADC_EOC;
reg [10:0] addr;
reg [7:0] wrBus;
reg we;
// Outputs
wire ADC_CS;
wire ADC_CSTART;
wire ADC_SCLK;
wire [7:0] rdBus;
// Bidirs
wire ADC_SDIN;
wire ADC_SDOUT;
// Instantiate the Unit Under Test (UUT)
ADC_peripheral uut (
.clk(clk),
.reset(reset),
.cs(cs),
.ADC_EOC(ADC_EOC),
.ADC_CS(ADC_CS),
.ADC_CSTART(ADC_CSTART),
.ADC_SCLK(ADC_SCLK),
.ADC_SDIN(ADC_SDIN),
.ADC_SDOUT(ADC_SDOUT),
.addr(addr),
.rdBus(rdBus),
.wrBus(wrBus),
.we(we)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
cs = 0;
ADC_EOC = 1;
addr = 0;
wrBus = 0;
we = 0;
// Wait 100 ns for global reset to finish
#100;
addr = 0;
wrBus = 1;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 1;
wrBus = 8;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 2;
wrBus = 0;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 3;
wrBus = 0;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 3;
wrBus = 8'h39;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 1;
#20;
while(rdBus[5])
begin
#20;
end
#100;
addr = 3;
wrBus = 8'h39;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 1;
#20;
while(rdBus[5])
begin
#20;
end
#100;
addr = 0;
wrBus = 2;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 1;
wrBus = 10;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 2;
wrBus = 0;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 3;
wrBus = 8'h2B;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 1;
#20;
while(rdBus[5])
begin
#20;
end
#100;
addr = 1;
wrBus = 15;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 3;
wrBus = 8'h2C;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 1;
#20;
while(rdBus[5])
begin
#20;
end
#100;
addr = 1;
wrBus = 20;
we = 1;
cs = 1;
#20;
addr = 0;
wrBus = 0;
we = 0;
cs = 0;
#20;
addr = 3;
wrBus = 8'h2D;
we = 1;
cs = 1;
#20;
addr = 3;
wrBus = 0;
we = 0;
cs = 1;
#20;
while(rdBus[5])
begin
#20;
end
#100;
end
// Match Xport 2.0 50 MHz clock on FPGA (20ns period)
always begin clk = ~clk; #10; end
endmodule