Merge branch 'master' of projects.qi-hardware.com:nn-usb-fpga
This commit is contained in:
Carlos Camargo
commit
987d098519
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@ -16,30 +16,27 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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// synchronize signals
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reg sncs, snwe;
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reg [10:0] buffer_addr;
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wire [8:0] addr2;
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reg [B:0] buffer_data;
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// interfaz fpga signals
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wire [10:0] addr;
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// bram interfaz signals
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reg we;
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wire we2;
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reg w_st=0;
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reg [B:0] wrBus;
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wire [B:0] rdBus;
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wire [B:0] wrBus2;
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wire [B:0] rdBus2;
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// interfaz fpga signals
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wire [10:0] addr;
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reg [25:0] counter;
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// Test : LED blinking
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always @(posedge clk) begin
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if (reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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led <=counter[25];
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if (reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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led <=counter[25];
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end
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// interefaz signals assignments
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@ -49,10 +46,10 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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// synchronize assignment
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always @(negedge clk)
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begin
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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end
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// write access cpu to bram
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@ -75,30 +72,34 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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endcase
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end
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(rdBus), // Port A 8-bit Data Output
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.DOB(rdBus2), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(wrBus), // Port A 8-bit Data Input
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.DIB(wrBus2), // Port B 8-bit Data Input
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.DIPA(1'b0), // Port A 1-bit parity Input
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.DIPB(1'b0), // Port-B 1-bit parity Input
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.ENA(1'b1), // Port A RAM Enable Input
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.ENB(1'b1), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(we), // Port A Write Enable Input
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.WEB(we2) ); // Port B Write Enable Input
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// Peripherals control
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wire [3:0] csN;
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wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
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assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000:
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4'b0100)
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: (buffer_addr[9]? 4'b0010:
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4'b0001);
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assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3:
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rdBus2)
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: (buffer_addr[9]? rdBus1:
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rdBus0);
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// Peripheral instantiation
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ADC_peripheral P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
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rdBus2, wrBus2, addr2);
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ADC_peripheral P1(
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.clk(clk),
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.reset(reset),
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.cs(csN[0]),
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.ADC_EOC(ADC_EOC),
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.ADC_CS(ADC_CS),
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.ADC_CSTART(ADC_CSTART),
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.ADC_SCLK(ADC_SCLK),
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.ADC_SDIN(ADC_SDIN),
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.ADC_SDOUT(ADC_SDOUT),
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.addr(buffer_addr[8:0]),
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.rdBus(rdBus0),
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.wrBus(wrBus),
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.we(we));
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endmodule
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@ -1,18 +1,21 @@
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`timescale 1ns / 1ps
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module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
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rdBus2, wrBus2, addr2);
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module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT,
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addr, rdBus, wrBus, we);
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input clk, reset, ADC_EOC;
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input [7:0] rdBus2;
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output we2, ADC_CS, ADC_CSTART, ADC_SCLK;
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output [7:0] wrBus2;
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output [8:0] addr2;
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input clk, reset, ADC_EOC, cs, we;
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input [8:0] addr;
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input [7:0] wrBus;
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output ADC_CS, ADC_CSTART, ADC_SCLK;
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output [7:0] rdBus;
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inout ADC_SDIN, ADC_SDOUT;
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reg we2=0, nSample=0;
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wire [7:0] rdBus2;
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reg [7:0] wrBus2;
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reg [8:0] addr2;
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wire we1;
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reg we2=0, nSample=0;
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reg [7:0] auto_count=0;
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reg [4:0] w_st2=0;
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reg [3:0] SPI_in_data=0;
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@ -22,8 +25,31 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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reg [7:0] buffer_rd1;
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reg [3:0] ADC_cmd;
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assign we1 = we & cs;
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assign ADC_CSTART = 1'b1;
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(rdBus), // Port A 8-bit Data Output
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.DOB(rdBus2), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(addr[8:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(wrBus), // Port A 8-bit Data Input
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.DIB(wrBus2), // Port B 8-bit Data Input
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.DIPA(1'b0), // Port A 1-bit parity Input
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.DIPB(1'b0), // Port-B 1-bit parity Input
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.ENA(1'b1), // Port A RAM Enable Input
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.ENB(1'b1), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(we1), // Port A Write Enable Input
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.WEB(we2) ); // Port B Write Enable Input
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// SPI comunication module instantiation
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reg ADC_SCLK_buffer = 0;
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reg ADC_SDIN_buffer = 0;
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@ -157,5 +183,6 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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//Sent clock divider for speed on SPI comunication
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10: begin clkdiv = rdBus2; w_st2 <= 0; end
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endcase
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end
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end
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endmodule
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@ -0,0 +1,36 @@
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CC = mipsel-openwrt-linux-gcc
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all: upload
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DEBUG = -O3 -g0
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COMMON_SOURCES = jz47xx_gpio.c jz47xx_mmap.c jz_adc_peripheral.c
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H_SOURCES = jz47xx_gpio.h jz47xx_mmap.h jz_adc_peripheral.h
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INCLUDE = -I.
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WARNINGS= -Wcast-align -Wpacked -Wpadded -Wall
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CCFLAGS = ${INCLUDE} ${DEBUG} ${WARNINGS}
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LDFLAGS =
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COMMON_OBJECTS = $(COMMON_SOURCES:.c=.o)
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NANO_IP = 192.168.254.101
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jz_test_adc: $(COMMON_OBJECTS)
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$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_test_adc.c -o jz_test_adc
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.c.o:
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$(CC) -c $(CCFLAGS) $< -o $@
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upload: jz_test_adc
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scp jz_test_adc root@$(NANO_IP):/root/
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clean:
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rm -f *.o jz_test_adc ${EXEC} *~
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indent:
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indent -bad -bap -nbc -bl -nce -i2 --no-tabs --line-length120 $(COMMON_SOURCES) $(H_SOURCES)
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@ -0,0 +1,108 @@
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/*
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JZ47xx GPIO at userspace
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Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
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||||
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||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <jz47xx_gpio.h>
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#include <jz47xx_mmap.h>
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#define JZ_GPIO_BASE 0x10010000
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void
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jz_gpio_as_output (JZ_PIO * pio, unsigned int o)
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{
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pio->PXFUNC = (1 << (o));
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pio->PXSELC = (1 << (o));
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pio->PXDIRS = (1 << (o));
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}
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void
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jz_gpio_as_input (JZ_PIO * pio, unsigned int o)
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{
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pio->PXFUNC = (1 << (o));
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pio->PXSELC = (1 << (o));
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pio->PXDIRC = (1 << (o));
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}
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void
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jz_gpio_set_pin (JZ_PIO * pio, unsigned int o)
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{
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pio->PXDATS = (1 << (o));
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}
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void
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jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o)
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{
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pio->PXDATC = (1 << (o));
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}
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|
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void
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jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val)
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{
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if (val == 0)
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pio->PXDATC = (1 << (o));
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else
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pio->PXDATS = (1 << (o));
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||||
}
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|
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unsigned int
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||||
jz_gpio_get_pin (JZ_PIO * pio, unsigned int o)
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{
|
||||
return (pio->PXPIN & (1 << o)) ? 1 : 0;
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||||
}
|
||||
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int
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||||
jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func)
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{
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||||
switch (func)
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{
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||||
case 0:
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||||
pio->PXFUNS = (1 << o);
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||||
pio->PXTRGC = (1 << o);
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||||
pio->PXSELC = (1 << o);
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||||
return 1;
|
||||
|
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case 1:
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||||
pio->PXFUNS = (1 << o);
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||||
pio->PXTRGC = (1 << o);
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||||
pio->PXSELS = (1 << o);
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||||
return 1;
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||||
|
||||
case 2:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGS = (1 << o);
|
||||
pio->PXSELC = (1 << o);
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||||
return 1;
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||||
}
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return 0;
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||||
}
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||||
|
||||
JZ_PIO *
|
||||
jz_gpio_map (int port)
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{
|
||||
JZ_PIO *pio;
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||||
|
||||
pio = (JZ_PIO *) jz_mmap (JZ_GPIO_BASE);
|
||||
pio = (JZ_PIO *) ((unsigned int) pio + port * 0x100);
|
||||
|
||||
return pio;
|
||||
}
|
||||
|
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@ -0,0 +1,84 @@
|
|||
/*
|
||||
JZ47xx GPIO at userspace
|
||||
|
||||
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#ifndef __jz47xx_gpio_h__
|
||||
#define __jz47xx_gpio_h__
|
||||
|
||||
#define JZ_GPIO_PORT_A 0
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||||
#define JZ_GPIO_PORT_B 1
|
||||
#define JZ_GPIO_PORT_C 2
|
||||
#define JZ_GPIO_PORT_D 3
|
||||
|
||||
typedef volatile unsigned int JZ_REG; /* Hardware register definition */
|
||||
|
||||
typedef struct _JZ_PIO
|
||||
{
|
||||
JZ_REG PXPIN; /* PIN Level Register */
|
||||
JZ_REG Reserved0;
|
||||
JZ_REG Reserved1;
|
||||
JZ_REG Reserved2;
|
||||
JZ_REG PXDAT; /* Port Data Register */
|
||||
JZ_REG PXDATS; /* Port Data Set Register */
|
||||
JZ_REG PXDATC; /* Port Data Clear Register */
|
||||
JZ_REG Reserved3;
|
||||
JZ_REG PXIM; /* Interrupt Mask Register */
|
||||
JZ_REG PXIMS; /* Interrupt Mask Set Reg */
|
||||
JZ_REG PXIMC; /* Interrupt Mask Clear Reg */
|
||||
JZ_REG Reserved4;
|
||||
JZ_REG PXPE; /* Pull Enable Register */
|
||||
JZ_REG PXPES; /* Pull Enable Set Reg. */
|
||||
JZ_REG PXPEC; /* Pull Enable Clear Reg. */
|
||||
JZ_REG Reserved5;
|
||||
JZ_REG PXFUN; /* Function Register */
|
||||
JZ_REG PXFUNS; /* Function Set Register */
|
||||
JZ_REG PXFUNC; /* Function Clear Register */
|
||||
JZ_REG Reserved6;
|
||||
JZ_REG PXSEL; /* Select Register */
|
||||
JZ_REG PXSELS; /* Select Set Register */
|
||||
JZ_REG PXSELC; /* Select Clear Register */
|
||||
JZ_REG Reserved7;
|
||||
JZ_REG PXDIR; /* Direction Register */
|
||||
JZ_REG PXDIRS; /* Direction Set Register */
|
||||
JZ_REG PXDIRC; /* Direction Clear Register */
|
||||
JZ_REG Reserved8;
|
||||
JZ_REG PXTRG; /* Trigger Register */
|
||||
JZ_REG PXTRGS; /* Trigger Set Register */
|
||||
JZ_REG PXTRGC; /* Trigger Set Register */
|
||||
JZ_REG Reserved9;
|
||||
JZ_REG PXFLG; /* Port Flag Register */
|
||||
JZ_REG PXFLGC; /* Port Flag clear Register */
|
||||
} JZ_PIO, *PJZ_PIO;
|
||||
|
||||
void jz_gpio_as_output (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_as_input (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_set_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val);
|
||||
|
||||
unsigned int jz_gpio_get_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
int jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func);
|
||||
|
||||
JZ_PIO *jz_gpio_map (int port);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* JZ47xx GPIO lines
|
||||
*
|
||||
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdlib.h>
|
||||
#include <termios.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <jz47xx_mmap.h>
|
||||
|
||||
|
||||
void *
|
||||
jz_mmap (off_t address)
|
||||
{
|
||||
int fd;
|
||||
|
||||
void *pio;
|
||||
|
||||
if ((fd = open ("/dev/mem", O_RDWR | O_SYNC)) == -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot open /dev/mem.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
pio = (void *) mmap (0, getpagesize (), PROT_READ | PROT_WRITE, MAP_SHARED, fd, address);
|
||||
|
||||
if (pio == (void *) -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot mmap.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
return pio;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* JZ47xx GPIO lines
|
||||
*
|
||||
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
|
||||
*/
|
||||
|
||||
#ifndef __jz47xx_mmap_h__
|
||||
#define __jz47xx_mmap_h__
|
||||
|
||||
#include <sys/mman.h>
|
||||
|
||||
void *jz_mmap (off_t address);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/* ADC Peripheral.c
|
||||
|
||||
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
|
||||
Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz_adc_peripheral.h"
|
||||
|
||||
void
|
||||
jz_adc_config(JZ_REG * addr, uchar BUFFER, uchar CLK_DIV, uchar CMD)
|
||||
{
|
||||
addr[0] = (BUFFER << 16) + (CLK_DIV<<8) + CMD;
|
||||
}
|
||||
|
||||
int
|
||||
jz_adc_check_buffer(JZ_REG * addr)
|
||||
{
|
||||
return addr[0]&0x00FF0000;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/* ADC Peripheral.h
|
||||
|
||||
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
|
||||
Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#ifndef __adc_peropheral_h__
|
||||
#define __adc_peropheral_h__
|
||||
|
||||
#include "jz47xx_gpio.h"
|
||||
|
||||
#define ADC_CMD_NONE 0x00 /* Nothing to do */
|
||||
#define ADC_CMD_SET_SPI_CLKDIV 0x90 /* Set clock divider for ADC sclk */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL0 0x50 /* Set channel 0 */
|
||||
#define ADC_CMD_READ_CHANNEL0 0x60 /* Read channel 0 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL1 0x51 /* Set channel 1 */
|
||||
#define ADC_CMD_READ_CHANNEL1 0x61 /* Read channel 1 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL2 0x52 /* Set channel 2 */
|
||||
#define ADC_CMD_READ_CHANNEL2 0x62 /* Read channel 2 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL3 0x53 /* Set channel 3 */
|
||||
#define ADC_CMD_READ_CHANNEL3 0x63 /* Read channel 3 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL4 0x54 /* Set channel 4 */
|
||||
#define ADC_CMD_READ_CHANNEL4 0x64 /* Read channel 4 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL5 0x55 /* Set channel 5 */
|
||||
#define ADC_CMD_READ_CHANNEL5 0x65 /* Read channel 5 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL6 0x56 /* Set channel 6 */
|
||||
#define ADC_CMD_READ_CHANNEL6 0x66 /* Read channel 6 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL7 0x57 /* Set channel 7 */
|
||||
#define ADC_CMD_READ_CHANNEL7 0x67 /* Read channel 8 */
|
||||
|
||||
#define ADC_CMD_SET_POWER_DOWN 0X58 /* Set ADC power down mode (1uA) */
|
||||
|
||||
#define ADC_CMD_SET_FAST_CONV 0X59 /* Initialize ADC Fast Convertion(<10us)*/
|
||||
|
||||
#define ADC_CMD_SET_LOW_CONV 0X5A /* Initialize ADC Fast Convertion(<40us)*/
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_1 0x5B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
|
||||
#define ADC_CMD_READ_AUTOSELFT_1 0x6B /* Read Autoselft ADC 1 (0x0200) */
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_2 0x5C /* Set Autoselft ADC (Vref-) */
|
||||
#define ADC_CMD_READ_AUTOSELFT_2 0x6C /* Read Autoselft ADC 2 (0x0000) */
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_3 0x5D /* Set Autoselft ADC (Vref+) */
|
||||
#define ADC_CMD_READ_AUTOSELFT_3 0x6D /* Read Autoselft ADC 3 (0x03FF) */
|
||||
|
||||
#define ADC_SPI_CLKDIV_MIN 0x09 /* 50/(2*9) -> 2.7MHz (MAX=2.8MHz) */
|
||||
#define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*255) -> 98.04KHz */
|
||||
|
||||
#define ADC_MAX_BUFFER 0xFE /* 254 reads/commands */
|
||||
|
||||
typedef unsigned char uchar;
|
||||
|
||||
void jz_adc_config(JZ_REG * addr, uchar BUFFER, uchar CLK_DIV, uchar CMD);
|
||||
|
||||
int jz_adc_check_buffer(JZ_REG * addr);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/* ADC TEST
|
||||
|
||||
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
|
||||
Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz47xx_gpio.h"
|
||||
#include "jz47xx_mmap.h"
|
||||
#include "jz_adc_peripheral.h"
|
||||
|
||||
#define TEST_PORT JZ_GPIO_PORT_B
|
||||
#define TEST_PIN 26
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
int i,j;
|
||||
JZ_PIO *pio;
|
||||
JZ_REG *virt_addr;
|
||||
|
||||
pio = jz_gpio_map (TEST_PORT);
|
||||
jz_gpio_as_func (pio, TEST_PIN, 0);
|
||||
|
||||
virt_addr = (JZ_REG *) (jz_mmap (0x13010000) + 0x18);
|
||||
|
||||
if (*virt_addr != 0x0FFF7700)
|
||||
{
|
||||
*virt_addr = 0x0FFF7700;
|
||||
printf ("Configuring CS2 32 bits and 0 WS: %08X\n", *virt_addr);
|
||||
}
|
||||
else
|
||||
printf ("CS2, already configured: %08X\n", *virt_addr);
|
||||
|
||||
virt_addr = (JZ_REG *) jz_mmap (0x14000000);
|
||||
|
||||
/*************************Clean FPGA RAM memory****************************/
|
||||
for (i = 0; i < 512; i++) //RAMB16_s9_s9 has 2048 bytes 8-bit
|
||||
{
|
||||
virt_addr[i] = 0x00000000; //Clean 4 register by cicle
|
||||
}
|
||||
|
||||
/****************Configure ADC register on FPGA RAM memory*****************/
|
||||
uchar LENB = 0x01; // 1 read/cmd
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_SPI_CLKDIV);
|
||||
usleep (100);
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_FAST_CONV);
|
||||
usleep (100);
|
||||
printf("\nADC in Fast Convertion Mode (10us) and Fs=9.8KHz (Min)\n");
|
||||
|
||||
LENB = ADC_MAX_BUFFER; // 254 read/cmd
|
||||
|
||||
/******************************* TEST 1 ***********************************/
|
||||
printf("\nINIT TEST1: Autoselft {(Vref+) - (Vref-)}/2 -> Return 0x0200 \n");
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_1);
|
||||
usleep (100);
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_1);
|
||||
printf("[%08X]", virt_addr[0]);
|
||||
while(jz_adc_check_buffer(virt_addr))
|
||||
{
|
||||
printf("[%08X]-", virt_addr[0]);
|
||||
fflush (stdout);
|
||||
usleep (10000);
|
||||
}
|
||||
for(i=1; i< LENB/2+1; i++)
|
||||
printf("[%08X]", virt_addr[i]);
|
||||
|
||||
/******************************* TEST 2 ***********************************/
|
||||
printf("\n\nINIT TEST2: Autoselft (Vref-) -> Return 0x0000 \n");
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_2);
|
||||
usleep (100);
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_2);
|
||||
while(jz_adc_check_buffer(virt_addr)){usleep (100);}
|
||||
for(i=1; i< LENB/2+1; i++)
|
||||
printf("[%08X]", virt_addr[i]);
|
||||
|
||||
/******************************* TEST 3 ***********************************/
|
||||
printf("\n\nINIT TEST3: Autoselft (Vref+) -> Return 0x03FF \n");
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_3);
|
||||
usleep (100);
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_3);
|
||||
while(jz_adc_check_buffer(virt_addr)){usleep (100);}
|
||||
for(i=1; i< LENB/2+1; i++)
|
||||
printf("[%08X]", virt_addr[i]);
|
||||
|
||||
printf("\n\nTESTS complete\n");
|
||||
|
||||
LENB = 0x01; // 1 read/cmd
|
||||
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_POWER_DOWN);
|
||||
printf("\nADC in Power Down Mode \n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue