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Adding bootloader for lm32

This commit is contained in:
carlos 2010-10-12 09:05:52 -05:00
parent 9da569a830
commit 9b75552c83
17 changed files with 820 additions and 139 deletions
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16
KICAD_design_files/SAKC_PCB_v2/SAKC.pro
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@ -1,5 +1,5 @@
update=Sat 09 Oct 2010 05:15:55 PM COT
last_client=cvpcb
update=Mon 11 Oct 2010 12:34:05 PM COT
last_client=pcbnew
[general]
version=1
RootSch=SAKC.sch
@ -73,6 +73,11 @@ LibName30=Design files/mcp3008
LibName31=Design files/o_analog
LibName32=Design files/tm2301n
LibName33=Design files/tl780-05ckttr
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=0
@ -92,6 +97,7 @@ TxtLar=120
MSegLar=79
LastNetListRead=
[pcbnew/libraries]
LibDir=./N_MODELS/
LibName1=./N_MODELS/D8
LibName2=./N_MODELS/R36
LibName3=./N_MODELS/R35
@ -268,10 +274,4 @@ LibName173=./N_MODELS/Y2
LibName174=./N_MODELS/Y3
LibName175=v-reg-2
LibName176=ref-packages
LibDir=./N_MODELS/
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms

1
lm32/logic/sakc/firmware/boot0-serial/crt0ram.d
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@ -1 +0,0 @@
crt0ram.o: crt0ram.S

BIN
lm32/logic/sakc/firmware/boot0-serial/crt0ram.o
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BIN
lm32/logic/sakc/firmware/boot0-serial/image
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127
lm32/logic/sakc/firmware/boot0-serial/image.map
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@ -1,127 +0,0 @@
Memory Configuration
Name Origin Length Attributes
bram 0x00000000 0x00001000
*default* 0x00000000 0xffffffff
Linker script and memory map
0x00000000 __DYNAMIC = 0x0
0x00000000 _BRAM_START = 0x0
0x00001000 _BRAM_SIZE = 0x1000
0x00001000 _BRAM_END = (_BRAM_START + _BRAM_SIZE)
.text 0x00000000 0x270
0x00000000 _ftext = .
*(.text .stub .text.* .gnu.linkonce.t.*)
.text 0x00000000 0x8c crt0ram.o
0x00000000 _start
0x00000060 irq_enable
0x0000006c irq_mask
0x00000078 irq_disable
0x00000084 jump
0x00000088 halt
.text 0x0000008c 0x104 main.o
0x0000008c read_uint32
0x000000d0 main
.text 0x00000190 0xe0 soc-hw.o
0x00000190 sleep
0x000001c8 tic_init
0x000001f0 uart_init
0x000001f4 uart_getchar
0x00000218 uart_putchar
0x0000023c uart_putstr
0x00000270 _etext = .
.rodata 0x00000270 0x1c
0x00000270 . = ALIGN (0x4)
0x00000270 _frodata = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.str1.4
0x00000270 0x1c main.o
*(.rodata1)
0x0000028c _erodata = .
.data 0x0000028c 0xc
0x0000028c . = ALIGN (0x4)
0x0000028c _fdata = .
*(.data .data.* .gnu.linkonce.d.*)
.data 0x0000028c 0x0 crt0ram.o
.data 0x0000028c 0x0 main.o
.data 0x0000028c 0xc soc-hw.o
0x0000028c uart0
0x00000290 timer0
0x00000294 gpio0
*(.data1)
0x000002a0 _gp = ALIGN (0x10)
*(.sdata .sdata.* .gnu.linkonce.s.*)
0x00000298 _edata = .
.bss 0x00000298 0x4
0x00000298 . = ALIGN (0x4)
0x00000298 _fbss = .
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
.bss 0x00000298 0x0 crt0ram.o
.bss 0x00000298 0x0 main.o
.bss 0x00000298 0x4 soc-hw.o
0x00000298 msec
*(COMMON)
0x0000029c _ebss = .
0x0000029c _end = .
0x00000ffc PROVIDE (_fstack, 0xffc)
LOAD crt0ram.o
LOAD main.o
LOAD soc-hw.o
OUTPUT(image elf32-lm32)
.debug_abbrev 0x00000000 0x219
.debug_abbrev 0x00000000 0xcd main.o
.debug_abbrev 0x000000cd 0x14c soc-hw.o
.debug_info 0x00000000 0x3d0
.debug_info 0x00000000 0x121 main.o
.debug_info 0x00000121 0x2af soc-hw.o
.debug_line 0x00000000 0x2d8
.debug_line 0x00000000 0x18f main.o
.debug_line 0x0000018f 0x149 soc-hw.o
.debug_frame 0x00000000 0xa0
.debug_frame 0x00000000 0x30 main.o
.debug_frame 0x00000030 0x70 soc-hw.o
.debug_loc 0x00000000 0xfb
.debug_loc 0x00000000 0xb7 main.o
.debug_loc 0x000000b7 0x44 soc-hw.o
.debug_pubnames
0x00000000 0xbc
.debug_pubnames
0x00000000 0x2b main.o
.debug_pubnames
0x0000002b 0x91 soc-hw.o
.debug_aranges 0x00000000 0x40
.debug_aranges
0x00000000 0x20 main.o
.debug_aranges
0x00000020 0x20 soc-hw.o
.debug_ranges 0x00000000 0x18
.debug_ranges 0x00000000 0x18 main.o
.debug_str 0x00000000 0x17b
.debug_str 0x00000000 0xb8 main.o
0xd0 (size before relaxing)
.debug_str 0x000000b8 0xc3 soc-hw.o
0x157 (size before relaxing)
.comment 0x00000000 0x11
.comment 0x00000000 0x11 main.o
0x12 (size before relaxing)
.comment 0x00000000 0x12 soc-hw.o

1
lm32/logic/sakc/firmware/boot0-serial/main.d
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@ -1 +0,0 @@
main.o: main.c soc-hw.h

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lm32/logic/sakc/firmware/boot0-serial/main.o
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1
lm32/logic/sakc/firmware/boot0-serial/soc-hw.d
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@ -1 +0,0 @@
soc-hw.o: soc-hw.c soc-hw.h

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lm32/logic/sakc/firmware/boot0-serial/soc-hw.o
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51
lm32/logic/sakc/firmware/loader_cain/Makefile Normal file
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@ -0,0 +1,51 @@
LM32_CC=lm32-elf-gcc
LM32_LD=lm32-elf-ld
LM32_OBJCOPY=lm32-elf-objcopy
LM32_OBJDUMP=lm32-elf-objdump
SREC2VRAM ?= ../../tools/srec2vram/srec2vram
VRAMFILE=image.ram
CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
SEGMENTS = -j .text -j .rodata -j .data
all: image.srec $(VRAMFILE)
crt0ram.o: crt0ram.S
$(LM32_CC) $(CFLAGS) -c crt0ram.S
main.o: main.c
$(LM32_CC) $(CFLAGS) -c main.c
soc-hw.o: soc-hw.c
$(LM32_CC) $(CFLAGS) -c soc-hw.c
xmodem.o: xmodem.c
$(LM32_CC) $(CFLAGS) -c xmodem.c
image: crt0ram.o main.o soc-hw.o xmodem.o linker.ld Makefile
$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o soc-hw.o xmodem.o
image.lst: image
$(LM32_OBJDUMP) -h -S $< > $@
image.bin: image
$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
image.srec: image image.lst
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
$(VRAMFILE): image.srec
$(SREC2VRAM) image.srec 0x0000000 0x1000 > $(VRAMFILE)
clean:
rm -f image image.lst image.bin image.srec image.map image.ram *.o *.d
DEPS := $(wildcard *.d)
ifneq ($(DEPS),)
include $(DEPS)
endif

249
lm32/logic/sakc/firmware/loader_cain/crt0ram.S Normal file
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@ -0,0 +1,249 @@
/*
* LatticeMico32 C startup code.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* Exception handlers - Must be 32 bytes long. */
.section .text, "ax", @progbits
.global _start
.global irq_enable, irq_disable, irq_set_mask, irq_get_mask
.global jump, halt
.global get_sp, get_gp
_start:
_reset_handler:
xor r0, r0, r0
wcsr IE, r0
mvhi r1, hi(_reset_handler)
ori r1, r1, lo(_reset_handler)
wcsr EBA, r1
calli _crt0
nop
nop
_breakpoint_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_ibuserror_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_watchpoint_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_dbuserror_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_divzero_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_interrupt_handler:
sw (sp+0), ra
calli _save_all
rcsr r1, IP
calli irq_handler
mvhi r1, 0xffff
ori r1, r1, 0xffff
wcsr IP, r1
bi _restore_all_and_eret
_scall_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_crt0:
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
/* Clear BSS */
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
.clearBSS:
be r1, r3, .callMain
sw (r1+0), r0
addi r1, r1, 4
bi .clearBSS
.callMain:
mvi r1, 0
mvi r2, 0
mvi r3, 0
calli main
irq_enable:
mvi r1, 1
wcsr IE, r1
ret
irq_disable:
mvi r1, 0
wcsr IE, r1
ret
irq_set_mask:
wcsr IM, r1
ret
irq_get_mask:
rcsr r1, IM
ret
jump:
b r1
halt:
bi halt
/* Save all registers onto the stack */
_save_all:
addi sp, sp, -128
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
sw (sp+16), r4
sw (sp+20), r5
sw (sp+24), r6
sw (sp+28), r7
sw (sp+32), r8
sw (sp+36), r9
sw (sp+40), r10
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
sw (sp+44), r11
sw (sp+48), r12
sw (sp+52), r13
sw (sp+56), r14
sw (sp+60), r15
sw (sp+64), r16
sw (sp+68), r17
sw (sp+72), r18
sw (sp+76), r19
sw (sp+80), r20
sw (sp+84), r21
sw (sp+88), r22
sw (sp+92), r23
sw (sp+96), r24
sw (sp+100), r25
sw (sp+104), r26
sw (sp+108), r27
#endif
sw (sp+120), ea
sw (sp+124), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+128)
sw (sp+116), r1
mv r1, sp
addi r1, r1, 128
sw (sp+112), r1
ret
/* Restore all registers and return from exception */
_restore_all_and_eret:
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
#endif
lw ra, (sp+116)
lw ea, (sp+120)
lw ba, (sp+124)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
eret
get_sp:
mv r1, sp
ret
get_gp:
mv r1, gp
ret

59
lm32/logic/sakc/firmware/loader_cain/linker.ld Normal file
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@ -0,0 +1,59 @@
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
__DYNAMIC = 0;
_RAM_START = 0x0000000;
_RAM_SIZE = 0x1000;
_RAM_END = _RAM_START + _RAM_SIZE;
MEMORY {
ram : ORIGIN = 0x0000000, LENGTH = 0x1000 /* 4k */
}
SECTIONS
{
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
} > ram
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_ebss = .;
_end = .;
} > ram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

55
lm32/logic/sakc/firmware/loader_cain/main.c Normal file
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@ -0,0 +1,55 @@
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include "soc-hw.h"
#define RAM_BASE 0x1000
unsigned int i, j,k; // Loop counter.
int main() {
int key, len, autoboot = 1, dispmenu = 1;
uart_init();
uart_putstr("Cain's bootloader!!! \n");
while(1){ /* loop forever until u-boot gets booted or the board is reset */
if(dispmenu){
uart_putstr("\n1: Upload program to RAM\n");
// uart_putstr("2: Upload u-boot to Dataflash\n");
// uart_putstr("3: Upload Kernel to Dataflash\n");
// uart_putstr("4: Start u-boot\n");
// uart_putstr("5: Upload Filesystem image\n");
// uart_putstr("6: Memory test\n");
dispmenu = 0;
}
key = uart_getchar();
autoboot = 0;
if(key == '1'){
len = rxmodem((char *)0x1000);
uart_putstr("Received ");
hexprint(len);
uart_putstr(" bytes\n");
jump(RAM_BASE);
// dispmenu = 1;
}
else if(key == '2'){
dispmenu = 1;
}
else{
uart_putstr("Invalid input\n");
dispmenu = 1;
}
}
while(1){ asm("nop;"); }
return (0);
}

153
lm32/logic/sakc/firmware/loader_cain/soc-hw.c Normal file
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@ -0,0 +1,153 @@
#include "soc-hw.h"
uart_t *uart0 = (uart_t *) 0xf0000000;
timer_t *timer0 = (timer_t *) 0xf0010000;
gpio_t *gpio0 = (gpio_t *) 0xF0020000;
isr_ptr_t isr_table[32];
void tic_isr();
/***************************************************************************
* IRQ handling
*/
void isr_null()
{
}
void irq_handler(uint32_t pending)
{
int i;
for(i=0; i<32; i++) {
if (pending & 0x01) (*isr_table[i])();
pending >>= 1;
}
}
void isr_init()
{
int i;
for(i=0; i<32; i++)
isr_table[i] = &isr_null;
}
void isr_register(int irq, isr_ptr_t isr)
{
isr_table[irq] = isr;
}
void isr_unregister(int irq)
{
isr_table[irq] = &isr_null;
}
/***************************************************************************
* TIMER Functions
*/
void msleep(uint32_t msec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000)*msec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
do {
//halt();
tcr = timer0->tcr1;
} while ( ! (tcr & TIMER_TRIG) );
}
void nsleep(uint32_t nsec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000000)*nsec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
do {
//halt();
tcr = timer0->tcr1;
} while ( ! (tcr & TIMER_TRIG) );
}
uint32_t tic_msec;
void tic_isr()
{
tic_msec++;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
}
void tic_init()
{
tic_msec = 0;
// Setup timer0.0
timer0->compare0 = (FCPU/10000);
timer0->counter0 = 0;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
isr_register(1, &tic_isr);
}
/***************************************************************************
* UART Functions
*/
void uart_init()
{
//uart0->ier = 0x00; // Interrupt Enable Register
//uart0->lcr = 0x03; // Line Control Register: 8N1
//uart0->mcr = 0x00; // Modem Control Register
// Setup Divisor register (Fclk / Baud)
//uart0->div = (FCPU/(57600*16));
}
char uart_getchar()
{
while (! (uart0->ucr & UART_DR)) ;
return uart0->rxtx;
}
void uart_putchar(char c)
{
while (uart0->ucr & UART_BUSY) ;
uart0->rxtx = c;
}
void uart_putstr(char *str)
{
char *c = str;
while(*c) {
uart_putchar(*c);
c++;
}
}
void hexprint(unsigned int hexval)
{
int digit[8], pos;
uart_putstr("0x");
for(pos = 0; pos < 8; pos++)
{
digit[pos] = (hexval & 0xF); /* last hexit */
hexval = hexval >> 4;
}
for(pos = 7; pos > -1; pos--)
{
if(digit[pos] < 0xA)
uart_putstr(digit[pos] + '0');
else
uart_putstr(digit[pos] + 'A' - 10);
}
uart_putchar(' ');
}

112
lm32/logic/sakc/firmware/loader_cain/soc-hw.h Normal file
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@ -0,0 +1,112 @@
#ifndef SPIKEHW_H
#define SPIKEHW_H
#define PROMSTART 0x00000000
#define RAMSTART 0x00000800
#define RAMSIZE 0x400
#define RAMEND (RAMSTART + RAMSIZE)
#define RAM_START 0x40000000
#define RAM_SIZE 0x04000000
#define FCPU 50000000
#define UART_RXBUFSIZE 32
/****************************************************************************
* Types
*/
typedef unsigned int uint32_t; // 32 Bit
typedef signed int int32_t; // 32 Bit
typedef unsigned char uint8_t; // 8 Bit
typedef signed char int8_t; // 8 Bit
/****************************************************************************
* Interrupt handling
*/
typedef void(*isr_ptr_t)(void);
void irq_enable();
void irq_disable();
void irq_set_mask(uint32_t mask);
uint32_t irq_get_mak();
void isr_init();
void isr_register(int irq, isr_ptr_t isr);
void isr_unregister(int irq);
/****************************************************************************
* General Stuff
*/
void halt();
void jump(uint32_t addr);
/****************************************************************************
* Timer
*/
#define TIMER_EN 0x08 // Enable Timer
#define TIMER_AR 0x04 // Auto-Reload
#define TIMER_IRQEN 0x02 // IRQ Enable
#define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR)
typedef struct {
volatile uint32_t tcr0;
volatile uint32_t compare0;
volatile uint32_t counter0;
volatile uint32_t tcr1;
volatile uint32_t compare1;
volatile uint32_t counter1;
} timer_t;
void msleep(uint32_t msec);
void nsleep(uint32_t nsec);
void tic_init();
/***************************************************************************
* GPIO0
*/
typedef struct {
volatile uint32_t ctrl;
volatile uint32_t dummy1;
volatile uint32_t dummy2;
volatile uint32_t dummy3;
volatile uint32_t in;
volatile uint32_t out;
volatile uint32_t oe;
} gpio_t;
/***************************************************************************
* UART0
*/
#define UART_DR 0x01 // RX Data Ready
#define UART_ERR 0x02 // RX Error
#define UART_BUSY 0x10 // TX Busy
typedef struct {
volatile uint32_t ucr;
volatile uint32_t rxtx;
} uart_t;
void uart_init();
void uart_putchar(char c);
void uart_putstr(char *str);
char uart_getchar();
void hexprint(unsigned int hexval);
/***************************************************************************
* Pointer to actual components
*/
extern timer_t *timer0;
extern uart_t *uart0;
extern gpio_t *gpio0;
extern uint32_t *sram0;
int rxmodem(unsigned char *dest);
#endif // SPIKEHW_H

132
lm32/logic/sakc/firmware/loader_cain/xmodem.c Normal file
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@ -0,0 +1,132 @@
/*
Copyright 2001, 2002 Georges Menie (www.menie.org)
Copyright 2004 Darrell Harmon modified to work in a bootloader
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "soc-hw.h"
#define SOH 0x01
#define EOT 0x04
#define ACK 0x06
#define NAK 0x15
/* CRC16 implementation acording to CCITT standards */
static const unsigned short crc16tab[256]= {
0x0000,0x1021,0x2042,0x3063,0x4084,0x50a5,0x60c6,0x70e7,
0x8108,0x9129,0xa14a,0xb16b,0xc18c,0xd1ad,0xe1ce,0xf1ef,
0x1231,0x0210,0x3273,0x2252,0x52b5,0x4294,0x72f7,0x62d6,
0x9339,0x8318,0xb37b,0xa35a,0xd3bd,0xc39c,0xf3ff,0xe3de,
0x2462,0x3443,0x0420,0x1401,0x64e6,0x74c7,0x44a4,0x5485,
0xa56a,0xb54b,0x8528,0x9509,0xe5ee,0xf5cf,0xc5ac,0xd58d,
0x3653,0x2672,0x1611,0x0630,0x76d7,0x66f6,0x5695,0x46b4,
0xb75b,0xa77a,0x9719,0x8738,0xf7df,0xe7fe,0xd79d,0xc7bc,
0x48c4,0x58e5,0x6886,0x78a7,0x0840,0x1861,0x2802,0x3823,
0xc9cc,0xd9ed,0xe98e,0xf9af,0x8948,0x9969,0xa90a,0xb92b,
0x5af5,0x4ad4,0x7ab7,0x6a96,0x1a71,0x0a50,0x3a33,0x2a12,
0xdbfd,0xcbdc,0xfbbf,0xeb9e,0x9b79,0x8b58,0xbb3b,0xab1a,
0x6ca6,0x7c87,0x4ce4,0x5cc5,0x2c22,0x3c03,0x0c60,0x1c41,
0xedae,0xfd8f,0xcdec,0xddcd,0xad2a,0xbd0b,0x8d68,0x9d49,
0x7e97,0x6eb6,0x5ed5,0x4ef4,0x3e13,0x2e32,0x1e51,0x0e70,
0xff9f,0xefbe,0xdfdd,0xcffc,0xbf1b,0xaf3a,0x9f59,0x8f78,
0x9188,0x81a9,0xb1ca,0xa1eb,0xd10c,0xc12d,0xf14e,0xe16f,
0x1080,0x00a1,0x30c2,0x20e3,0x5004,0x4025,0x7046,0x6067,
0x83b9,0x9398,0xa3fb,0xb3da,0xc33d,0xd31c,0xe37f,0xf35e,
0x02b1,0x1290,0x22f3,0x32d2,0x4235,0x5214,0x6277,0x7256,
0xb5ea,0xa5cb,0x95a8,0x8589,0xf56e,0xe54f,0xd52c,0xc50d,
0x34e2,0x24c3,0x14a0,0x0481,0x7466,0x6447,0x5424,0x4405,
0xa7db,0xb7fa,0x8799,0x97b8,0xe75f,0xf77e,0xc71d,0xd73c,
0x26d3,0x36f2,0x0691,0x16b0,0x6657,0x7676,0x4615,0x5634,
0xd94c,0xc96d,0xf90e,0xe92f,0x99c8,0x89e9,0xb98a,0xa9ab,
0x5844,0x4865,0x7806,0x6827,0x18c0,0x08e1,0x3882,0x28a3,
0xcb7d,0xdb5c,0xeb3f,0xfb1e,0x8bf9,0x9bd8,0xabbb,0xbb9a,
0x4a75,0x5a54,0x6a37,0x7a16,0x0af1,0x1ad0,0x2ab3,0x3a92,
0xfd2e,0xed0f,0xdd6c,0xcd4d,0xbdaa,0xad8b,0x9de8,0x8dc9,
0x7c26,0x6c07,0x5c64,0x4c45,0x3ca2,0x2c83,0x1ce0,0x0cc1,
0xef1f,0xff3e,0xcf5d,0xdf7c,0xaf9b,0xbfba,0x8fd9,0x9ff8,
0x6e17,0x7e36,0x4e55,0x5e74,0x2e93,0x3eb2,0x0ed1,0x1ef0
};
unsigned short crc16_ccitt(const void *buf, int len)
{
int counter;
unsigned short crc = 0;
for( counter = 0; counter < len; counter++)
crc = (crc<<8) ^ crc16tab[((crc>>8) ^ *(char *)buf++)&0x00FF];
return crc;
}
int rxmodem(unsigned char *dest)
{
unsigned long *ptr = (unsigned long *) 0x0;
unsigned short crc, tcrc;
int i, pid = 1, len = 0;
for (i = 0; i < 0x100000; i++)
{
*ptr = 0;
ptr++;
}
uart_putstr("Receiving Xmodem transfer\n");
uart_getchar ();
for(i = 0; i < 0x20000000; i++) { asm("nop;"); }
uart_putchar ('C');
while(1)
{
int c, pid1, pid2;
c = uart_getchar ();
if (c != SOH)
{
if (c == EOT)
{
uart_putchar (ACK);
return len;
}
else
return 0;
}
pid1 = uart_getchar ();
pid2 = uart_getchar ();
if ((pid1 & 0xFF) != (~pid2 & 0xFF))
return 0;
if (pid1 != pid)
return 0;
for (i = 0; i < 130; i++)
*dest++ = uart_getchar ();
crc = crc16_ccitt (dest - 130, 128);
tcrc = (*(dest - 2)<<8) + *(dest - 1);
if (crc != tcrc)
return 0;
else
{
pid = (pid + 1) & 0xFF;
dest -= 2;
len += 128;
uart_putchar (ACK);
}
}
}

2
lm32/logic/sakc/system.v
View File

@ -6,7 +6,7 @@
module system
#(
parameter bootram_file = "../firmware/boot0-serial/image.ram",
parameter bootram_file = "../firmware/loader_cain/image.ram",
parameter clk_freq = 50000000,
parameter uart_baud_rate = 57600
) (